See Input Termination for proper input terminations, dependent on single-ended or differential inputs.

See LVDS Output Termination for output termination schemes depending on the receiver application.

Unused outputs should be terminated differentially with a 100-Ω resistor or disabled through OUTx_EN register control (see Table 9-7) for optimum performance. Outputs may be left unterminated, but will result in slight degradation in performance (Output AC common-mode V_OS ) in the outputs being used.

In this example, the PHY, ASIC, and FPGA or CPU require different schemes. Power-supply filtering and bypassing is critical for low-noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board (SCAU043).