ZHCSSI1D august   2008  – august 2023 DAC5311 , DAC6311 , DAC7311

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements
    7. 7.7  Timing Diagrams
    8. 7.8  Typical Characteristics: AVDD = 5 V
    9. 7.9  Typical Characteristics: AVDD = 3.6 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Input Shift Register
        2. 8.5.1.2 SYNC Interrupt
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Microprocessor Interfacing
        1. 9.1.1.1 DACx311 to 8051 Interface
        2. 9.1.1.2 DACx311 to Microwire Interface
        3. 9.1.1.3 DACx311 to 68HC11 Interface
    2. 9.2 Typical Applications
      1. 9.2.1 Loop Powered Transmitter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Using the REF5050 as a Power Supply for the DACx311
      3. 9.2.3 Bipolar Operation Using the DACx311
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information

7.6 Timing Requirements

at –40°C to 125°C, and AVDD = 2 V to 5.5 V (unless otherwise noted)(1)

MIN NOM MAX UNIT
f(SCLK) Serial clock frequency AVDD = 2.0 V to 3.6 V 20 MHz
AVDD = 3.6 V to 5.5 V 50
t1 SCLK cycle time AVDD = 2.0 V to 3.6 V 50 ns
AVDD = 3.6 V to 5.5 V 20
t2 SCLK high time AVDD = 2.0 V to 3.6 V 25 ns
AVDD = 3.6 V to 5.5 V 10
t3 SCLK low time AVDD = 2.0 V to 3.6 V 25 ns
AVDD = 3.6 V to 5.5 V 10
t4 SYNC to SCLK rising edge setup time AVDD = 2.0 V to 3.6 V 0 ns
AVDD = 3.6 V to 5.5 V 0
t5 Data setup time AVDD = 2.0 V to 3.6 V 5 ns
AVDD = 3.6 V to 5.5 V 5
t6 Data hold time AVDD = 2.0 V to 3.6 V 4.5 ns
AVDD = 3.6 V to 5.5 V 4.5
t7 SCLK falling edge to SYNC rising edge AVDD = 2.0 V to 3.6 V 0 ns
AVDD = 3.6 V to 5.5 V 0
t8 Minimum SYNC high time AVDD = 2.0 V to 3.6 V 50 ns
AVDD = 3.6 V to 5.5 V 20
t9 16th SCLK falling edge to SYNC falling edge AVDD = 2.0 V to 3.6 V 100 ns
AVDD = 3.6 V to 5.5 V 100
t10 SYNC rising edge to 16th SCLK falling edge
(for successful SYNC interrupt)		 AVDD = 2.0 V to 3.6 V 15 ns
AVDD = 3.6 V to 5.5 V 15
(1) All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH) / 2.
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