ZHCSSI1D august 2008 – august 2023 DAC5311 , DAC6311 , DAC7311
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements
- 7.7 Timing Diagrams
- 7.8 Typical Characteristics: AVDD = 5 V
- 7.9 Typical Characteristics: AVDD = 3.6 V
- 7.10 Typical Characteristics: AVDD = 2.7 V
- 8 Detailed Description
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
9.1.1.3 DACx311 to 68HC11 Interface
Figure 9-3 shows a serial interface between the DACx311 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DACx311, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to what was done for the 8051.
Figure 9-3 DACx311 to 68HC11 InterfaceConfigure the 68HC11 so that the CPOL bit is 0 and the CPHA bit is 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is taken low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data are transmitted MSB first. To load data to the DACx311, PC7 is held low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure.