米6体育平台手机版

ZHCSTB0E February 2010 – November 2023 UCC27321-Q1 , UCC27322-Q1

PRODUCTION DATA

7.5 Electrical Characteristics

V_DD = 4.5 V to 15 V, T_J = T_A = –40°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_DD	Static operating current	UCC27321-Q1	IN = Low, ENBL = Low, V_DD = 15 V		150	225	µA
			IN = Low, ENBL = Low, V_DD = 15 V		440	650
			IN = High, ENBL = Low, V_DD = 15 V		370	550
			IN = High, ENBL = Low, V_DD = 15 V		370	550
		UCC27322-Q1	IN = Low, ENBL = High, V_DD = 15 V		150	225
			IN = Low, ENBL = High, V_DD = 15 V		450	650
			IN = High, ENBL = High, V_DD = 15 V		75	125
			IN = High, ENBL = High, V_DD = 15 V		675	1000
INPUT (IN)
V_IH	Logic 1 input threshold			1.6	2.2	2.5	V
V_IL	Logic 0 input threshold			1.1	1.8	2.0	V
	Input current	0 V ≤ V_IN ≤ V_DD		–10	0	10	µA
OUTPUT (OUT)
	Peak output current⁽¹⁾	V_DD = 14 V			9		A
R_OH	Output resistance high⁽²⁾	I_OUT = –10 mA			0.6	1.5	Ω
R_OL	Output resistance low⁽²⁾	I_OUT = 10 mA			0.4	1	Ω
ENABLE (ENBL)
V_{EN_H}	Enable rising threshold voltage	Low-to-high transitions		1.5	2.2	2.7	V
V_{EN_L}	Enable falling threshold voltage	High-to-low transition		1.1	1.65	2	V
	Hysteresis			0.18	0.55	0.9	V
R_(ENBL)	Enable impedance	V_DD = 14 V, ENBL = Low		75	100	145	kΩ
t_D3	Propagation delay time	C_LOAD = 10 nF (see Figure 7-2)			60	95	ns
t_D4	Propagation delay time	C_LOAD = 10 nF (see Figure 7-2)			60	95	ns

(1) Parameter not tested in production

(2) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.