ZHCSU66J August 2001 – December 2023 UCC29002 , UCC39002
PRODUCTION DATA
- 1
- 1特性
- 2应用
- 3说明
- 4Pin Configuration and Functions
- 5Specifications
-
6Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Differential Current-Sense Amplifier (CS+, CS−, CSO)
- 6.3.2 Load-Share Bus Driver Amplifier (CSO, LS)
- 6.3.3 Load-Share Bus Receiver Amplifier (LS)
- 6.3.4 Error Amplifier (EAO)
- 6.3.5 Adjust Amplifier Output (ADJ)
- 6.3.6 Enable Function (CS+, CS−)
- 6.3.7 Fault Protection on LS Bus
- 6.3.8 Start-Up and Adjust Logic
- 6.3.9 Bias Input and Bias_OK Circuit (VDD)
- 6.4 Device Functional Modes
- 7Application and Implementation
- 8Device and Documentation Support
- 9Revision History
- Mechanical, Packaging, and Orderable Information
6.3.6 Enable Function (CS+, CS−)
The two inputs of the current-sense amplifier are also used with an Enable Comparator to implement an ENABLE function in the UCC29002 device. During normal operation, the difference between CS− and CS+ voltages is very small and the internal -0.5V offset added between the CS− pin and the inverting input of the comparator ensures that the UCC29002 is always enabled.
Figure 6-1 Enable
ComparatorBy forcing the CS− pin at least 0.5V higher than the CS+ pin, the ENABLE signal becomes false and the UCC29002 is set into a disabled mode. While disabled, the UCC29002 disconnects from the load-share bus and the Adjust amplifier current is forced to zero.
When using high-side current-sensing (RSHUNT located in the module output voltage rail), CS− must not be forced higher than 0.3V above VDD. Instead, in this configuration CS+ should be pulled at least 0.5V below CS− to disable the UCC29002.
The ENABLE signal is combined with the BIAS OK signal (logical AND function) and affects the UCC29002 operating mode through the Start-Up and Adjust Logic block.