ZHCSWR1H December   2009  – July 2024 DRV8412

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Package Heat Dissipation Ratings
    6. 5.6 Package Power Deratings (DRV8412) #GUID-2A6DB468-D895-404F-A2E6-05A442AE2834/SLES2429141
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Error Reporting
      2. 6.3.2 Device Protection System
        1. 6.3.2.1 Bootstrap Capacitor Undervoltage Protection
        2. 6.3.2.2 Overcurrent (OC) Protection
        3. 6.3.2.3 Overtemperature Protection
        4. 6.3.2.4 Undervoltage Protection (UVP) and Power-On Reset (POR)
      3. 6.3.3 Device Reset
    4. 6.4 Device Functional Modes
  8.   Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Full Bridge Mode Operation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Motor Voltage
          2. 7.2.1.2.2 Current Requirement of 12V Power Supply
          3. 7.2.1.2.3 Voltage of Decoupling Capacitor
          4. 7.2.1.2.4 Overcurrent Threshold
          5. 7.2.1.2.5 Sense Resistor
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Parallel Full Bridge Mode Operation
      3. 7.2.3 Stepper Motor Operation
      4. 7.2.4 TEC Driver
      5. 7.2.5 LED Lighting Driver
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
      2. 7.3.2 Power Supplies
      3. 7.3.3 System Power-Up and Power-Down Sequence
        1. 7.3.3.1 Powering Up
        2. 7.3.3.2 Powering Down
      4. 7.3.4 System Design Recommendations
        1. 7.3.4.1 VREG Pin
        2. 7.3.4.2 VDD Pin
        3. 7.3.4.3 OTW Pin
        4. 7.3.4.4 Mode Select Pin
        5. 7.3.4.5 Parallel Mode Operation
        6. 7.3.4.6 TEC Driver Application
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Material Recommendation
        2. 7.4.1.2 Ground Plane
        3. 7.4.1.3 Decoupling Capacitor
        4. 7.4.1.4 AGND
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Current Shunt Resistor
      3. 7.4.3 Thermal Considerations
        1. 7.4.3.1 DRV8412 Thermal Via Design Recommendation
  9. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3. 7.3 Trademarks
    4. 7.4 静电放电警告
    5. 7.5 术语表
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

7.3.3.1 Powering Up

The DRV841x2 does not require a power-up sequence. The outputs of the H-bridges remain in a high impedance state until the gate-drive supply voltage GVDD_X and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, holding RESET_AB and RESET_CD in a low state while powering up the device is recommended. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.
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