Two reset pins are provided for independent control of half-­bridges A/B and C/D. When RESET_AB is asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise, asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high- impedance state. To accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak pulldown of the half-bridge outputs.

A rising-edge transition on reset input allows the device to resume operation after a shut-down fault. For example, when either or both half-bridge A and B have OC shutdown, a low to high transition of RESET_AB pin clears the fault and FAULT pin; when either or both half-bridge C and D have OC shutdown, a low to high transition of RESET_CD pin will clear the fault and FAULT pin as well. When an OTSD occurs, both RESET_AB and RESET_CD need to have a low to high transition to clear the fault and FAULT signal.