ZHCSWR1H December   2009  – July 2024 DRV8412

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Package Heat Dissipation Ratings
    6. 5.6 Package Power Deratings (DRV8412) #GUID-2A6DB468-D895-404F-A2E6-05A442AE2834/SLES2429141
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Error Reporting
      2. 6.3.2 Device Protection System
        1. 6.3.2.1 Bootstrap Capacitor Undervoltage Protection
        2. 6.3.2.2 Overcurrent (OC) Protection
        3. 6.3.2.3 Overtemperature Protection
        4. 6.3.2.4 Undervoltage Protection (UVP) and Power-On Reset (POR)
      3. 6.3.3 Device Reset
    4. 6.4 Device Functional Modes
  8.   Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Full Bridge Mode Operation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Motor Voltage
          2. 7.2.1.2.2 Current Requirement of 12V Power Supply
          3. 7.2.1.2.3 Voltage of Decoupling Capacitor
          4. 7.2.1.2.4 Overcurrent Threshold
          5. 7.2.1.2.5 Sense Resistor
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Parallel Full Bridge Mode Operation
      3. 7.2.3 Stepper Motor Operation
      4. 7.2.4 TEC Driver
      5. 7.2.5 LED Lighting Driver
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
      2. 7.3.2 Power Supplies
      3. 7.3.3 System Power-Up and Power-Down Sequence
        1. 7.3.3.1 Powering Up
        2. 7.3.3.2 Powering Down
      4. 7.3.4 System Design Recommendations
        1. 7.3.4.1 VREG Pin
        2. 7.3.4.2 VDD Pin
        3. 7.3.4.3 OTW Pin
        4. 7.3.4.4 Mode Select Pin
        5. 7.3.4.5 Parallel Mode Operation
        6. 7.3.4.6 TEC Driver Application
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Material Recommendation
        2. 7.4.1.2 Ground Plane
        3. 7.4.1.3 Decoupling Capacitor
        4. 7.4.1.4 AGND
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Current Shunt Resistor
      3. 7.4.3 Thermal Considerations
        1. 7.4.3.1 DRV8412 Thermal Via Design Recommendation
  9. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3. 7.3 Trademarks
    4. 7.4 静电放电警告
    5. 7.5 术语表
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

5.7 Electrical Characteristics

TA = 25°C, PVDD = 50V, GVDD = VDD = 12V, fSw = 400kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREGVoltage regulator, only used as a reference nodeVDD = 12 V2.953.33.65V
IVDDVDD supply currentIdle, reset mode912mA
Operating, 50% duty cycle10.5
IGVDD_XGate supply current per half-bridgeReset mode1.72.5mA
Operating, 50% duty cycle8
IPVDD_XHalf-bridge X (A, B, C, or D) idle currentReset mode0.71mA
OUTPUT STAGE
RDS(on)MOSFET drain-to-source resistance, low side (LS)TJ = 25°C, GVDD = 12 V, Includes metallization bond wire and pin resistance110mΩ
MOSFET drain-to-source resistance, high side (HS)TJ = 25°C, GVDD = 12 V, Includes metallization bond wire and pin resistance110
VFDiode forward voltage dropTJ = 25°C - 125°C, IO = 5 A1V
tROutput rise timeResistive load, IO = 5 A14ns
tFOutput fall timeResistive load, IO = 5 A14
tPD_ONPropagation delay when FET is onResistive load, IO = 5 A38
tPD_OFFPropagation delay when FET is offResistive load, IO = 5 A38
tDTDead time between HS and LS FETsResistive load, IO = 5 A5.5
I/O PROTECTION
Vuvp,GGate supply voltage GVDD_X undervoltage protection threshold8.5V
Vuvp,hyst(1)Hysteresis for gate supply undervoltage event0.8
OTW(1)Overtemperature warning115125135°C
OTWhyst(1)Hysteresis temperature to reset OTW event25
OTSD(1)Overtemperature shut down150
OTE-OTWdifferential(1)OTE-OTW overtemperature detect temperature difference25
OTSDHYST(1)Hysteresis temperature for FAULT to be released following an OTSD event25
IOCOvercurrent limit protectionResistor—programmable, nominal, ROCP = 27 kΩ9.7A
IOCTOvercurrent response timeTime from application of short condition to Hi-Z of affected FET(s)250ns
RPDInternal pulldown resistor at the output of each half-bridgeConnected when RESET_AB or RESET_CD is active to provide bootstrap capacitor charge1kΩ
STATIC DIGITAL SPECIFICATIONS
VIHHigh-level input voltagePWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M323.6V
VIHHigh-level input voltageRESET_AB, RESET_CD25.5
VILLow-level input voltagePWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD0.8
llkgInput leakage current–100100μA
OTW / FAULT
RINT_PUInternal pullup resistance, OTW to VREG, FAULT to VREG202635kΩ
VOHHigh-level output voltageInternal pullup resistor only2.953.33.65V
External pullup of 4.7 kΩ to 5 V4.55
VOLLow-level output voltageIO = 4 mA0.20.4
(1) Specified by design
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