ZHCU032K December 2004 – August 2022 MSP430AFE221 , MSP430AFE222 , MSP430AFE223 , MSP430AFE231 , MSP430AFE232 , MSP430AFE233 , MSP430AFE251 , MSP430AFE252 , MSP430AFE253 , MSP430F2001 , MSP430F2002 , MSP430F2003 , MSP430F2011 , MSP430F2012 , MSP430F2013 , MSP430F2101 , MSP430F2111 , MSP430F2112 , MSP430F2121 , MSP430F2122 , MSP430F2131 , MSP430F2132 , MSP430F2132-EP , MSP430F2232 , MSP430F2234 , MSP430F2252 , MSP430F2252-Q1 , MSP430F2254 , MSP430F2272 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274-EP , MSP430F233 , MSP430F2330 , MSP430F235 , MSP430F2350 , MSP430F2370 , MSP430F2410 , MSP430F2416 , MSP430F2417 , MSP430F2418 , MSP430F2419 , MSP430F247 , MSP430F2471 , MSP430F248 , MSP430F2481 , MSP430F249 , MSP430F2491 , MSP430F2616 , MSP430F2617 , MSP430F2618 , MSP430F2619 , MSP430G2001 , MSP430G2101 , MSP430G2102 , MSP430G2111 , MSP430G2112 , MSP430G2121 , MSP430G2131 , MSP430G2132 , MSP430G2152 , MSP430G2153 , MSP430G2201 , MSP430G2201-Q1 , MSP430G2202 , MSP430G2203 , MSP430G2210 , MSP430G2211 , MSP430G2212 , MSP430G2213 , MSP430G2221 , MSP430G2230 , MSP430G2231 , MSP430G2231-Q1 , MSP430G2232 , MSP430G2233 , MSP430G2252 , MSP430G2253 , MSP430G2302 , MSP430G2303 , MSP430G2312 , MSP430G2313 , MSP430G2332 , MSP430G2333 , MSP430G2352 , MSP430G2353 , MSP430G2402 , MSP430G2403 , MSP430G2412 , MSP430G2413 , MSP430G2432 , MSP430G2433 , MSP430G2444 , MSP430G2452 , MSP430G2453 , MSP430G2513 , MSP430G2533 , MSP430G2544 , MSP430G2553 , MSP430G2744 , MSP430G2755 , MSP430G2855 , MSP430G2955 , MSP430TCH5E
当主器件发送的从器件地址和带有一个设置 R/W 位的其自身地址相匹配时,从器件进入发送模式。受控传输器依靠主器件产生的时钟脉冲信号在 SDA 上移位传输串行数据。从器件不能产生时钟时钟但是当发送完一个字节后需要 CPU 的干预时,从器件能够保持 SCL 为低电平。
如果主器件向从器件器件请求数据,USCI 模块会自动配置为发送模式,并置位 UCTR 和 UCBxTXIFG。在数据未写入发送缓存 UCBxTXBUF之前,SCL 时钟线一直保持低电平。当地址被响应后,清除 UCSTTIFG 标志,然后开始传输数据。一旦数据被转移到移位寄存器,UCTXIFG 将再次被置位。被主器件确认之后,下一个被写入 UCBxTXBUF 中的字节数据开始传输,或发送缓冲区为空,通过一直保持 SCL 为低电平直到新的数据被写到 UCBxTXBUF 内,在应答周期内总线被挂起。假如主器件通过一个停止条件成功发送了一个 NACK 信号,则 UCSTPIFG 被置位。如若 NACK 被一个重复起始条件成功发送,则USCI I2C 状态机返回至其地址接收状态。
图 17-9给出了受控发送器运行。