There are 4 main voltage rails that are monitored: 5 V, 20 V, 40 V, and ±5 V. Each rail is measured using the same architecture; starting with a voltage divider to scale the voltage down to within the input limitation of the operational amplifier (op amp), followed by a buffer stage allowing for high input impedance on the sensor side and a low impedance on the ADC side to ensure fast settling time.

There are two options to effectively measure the lower limit of the circuits and remain within the input voltage limitations of the op amp which is approximately 200 mV greater than the negative voltage supply rail.

For the external ADC variation and internal ADC variation, the voltage reference for the offset voltage is the same as the voltage reference for their respective ADC (external, 5 V or internal, 2.5 V). This negates any noise and inaccuracies created by the offset voltage. The second option includes an external negative bias on the negative voltage supply pin of the op amp to decrease the lower input limitation of the op amp.

To help with calculations of the circuit, the Analog Engineer's Calculator was used to calculate resistor and capacitor values. Table 2-3 and Table 2-4 show the calculated values of R_a, R_b, and R_c determined from the gain and voltage output range of the circuit. The calculated resistor values results with a 0-V input having a 0.2-V output, and the maximum voltage input resulting in a 4.8-V output and 2.5-V output for the external ADC or internal ADC configuration, respectively.

R_CB and C_CB are charge bucket circuits that help with the settling time of the output signal to drive the ADC128S102QML-SP. Due to the MUXed input of the ADC128S102QML-SP the acquisition and conversion time has to be properly calculated. In this design, the desired bandwidth is 5 kHz per channel. This results in 40 kHz of accumulated bandwidth. Finally, to fulfill the Nyquist Theorem, the resulting sampling rate is double the needed bandwidth, resulting in a final sample rate of 80 kHz or 12.5 µs per sample which leads to a minimum conversion time of 10.156 µs and an acquisition time of 2.3437 µs. To help with calculations of the circuit, the Analog Engineer's Calculator was used to calculate R_CB and C_CB.

Figure 2-3 Voltage Monitoring - Internal ADC Configuration