The reference design SSR topology uses the high impedance voltage translator connected between the digital isolator and the SSR MOSFET gate. Figure 2-7 illustrates the high-impedance voltage translator consists of a PNP transistor (Q_P) and an NPN transistor (Q_N).

When SSR is switching, the voltage across the blocking diode (D) changes. For a 24-VAC supply, the peak voltage across the blocking diode could be as high as 41 V (considering 20% tolerance on the AC voltage supply). The same voltage level appears across the PNP transistor (Q_P), and hence the PNP transistor has to be rated more than 41 V with sufficient voltage margin. If the digital isolator is used directly to turn on the SSR, the higher voltage will damage the output structure of isolator.

The NPN and the PNP transistor circuit forms the voltage translator circuit, translating the 5 V at the digital isolator output to a higher voltage for the MOSFET gate drive. It is also required that the off-state leakage of the PNP transistor has to be very low so that the resulting voltage drop across the resistor between the gate and source of the SSR MOSFET, is sufficiently less than the worst-case gate threshold voltage of MOSFETs.