Figure 1-1 shows the block diagram of the proposed multichannel phase-synchronized clock solution interface with multiple RF sampling transceivers. The AFE7950EVM interfaces with the TSW14J56 EVM data capture board through the FMC adapter card. A device clock and SYSREF to the AFE7950EVMs are provided by the LMX2820 using the length-matched cables and FPGA reference clocks and SYSREF provided through the LMK04832.

Figure 1-1 Block Diagram of Interface Between Clocking Board, AFE7950 EVM, FMC Adapter Board, and TSW14J56 Board