ZHCUBT9A January   2024  – September 2024

 

  1.   1
  2.   说明
  3.   特性
  4.   4
  5. 1评估模块概述
    1.     前言：使用前必读
      1. 1.1.1 Sitara MCU+ Academy
      2. 1.1.2 如果您需要协助
    2. 1.1 引言
    3. 1.2 套件内容
    4. 1.3 器件信息
  6. 2硬件
    1. 2.1 组件标识
    2. 2.2 电源要求
      1. 2.2.1 电源树
    3. 2.3 功能方框图
    4. 2.4 接头信息
    5. 2.5 测试点
    6. 2.6 接口
      1. 2.6.1 以太网接口
        1. 2.6.1.1 工业以太网 PHY
        2. 2.6.1.2 工业以太网 PHY Strap 配置电阻器
        3. 2.6.1.3 RJ45 连接器中的 LED 指示
        4. 2.6.1.4 Multi-Connector Addressing
    7. 2.7 集成指南
      1. 2.7.1 电路板尺寸
      2. 2.7.2 DF40GB 连接器
      3. 2.7.3 安装孔
      4. 2.7.4 RJ45 以太网连接器
  7. 3硬件设计文件
  8. 4其他信息
    1. 4.1 商标
  9. 5参考文献
    1. 5.1 参考文档
    2. 5.2 兼容的 Sitara™ MCU AM2x EVM
  10. 6修订历史记录

2.6.1.4 Multi-Connector Addressing

For Sitara AM2x EVMs with more than one Ethernet add-on board connector, each DP83826-EVM-AM2 requires a different EEPROM I2C address and PHY address. The EEPROM A0 and A2 nets, set by pull resistors on the main Sitara AM2x EVM drive the PHY address nets via a FET network implemented on the DP83826-EVM-AM2. Table 2-5 details the multi-connector I2C and PHY addressing scheme implemented on the add-on PHY board.

Note:
  • The EEPROM I2C address bits A2 and A0 are driven via pull resistors on the main Sitara AM2x EVM. The pull resistors for each enumerated connector follow the table below.
  • EEPROM I2C address bit A1 will always be pulled high to VDDIO on the add-on board
  • The EEPROM I2C address is defined by the following 8 bits: 8b1010[A2][A1][A0][R/W]
  • Pulls to VDDIO/GND are via 10kOhm resistor
  • All EVMs with a single connector are configured as CONNECTOR_0

Table 2-5 Multi-Connector I2C / PHY Addressing Scheme
Connector_# EEPROM_A2 (connector pin 37) EEPROM_A1 EEPROM_A0 (connector pin 47) I2C Address DP83826 PHY Address
Pull A2 Pull A1 Pull A0
CONNECTOR_0 GND 0 VDDIO 1 GND 0 0x52 3b001
CONNECTOR_1 GND 0 VDDIO 1 VDDIO 1 0x53 3b011
CONNECTOR_2 VDDIO 1 VDDIO 1 GND 0 0x56 3b101
CONNECTOR_3 VDDIO 1 VDDIO 1 VDDIO 1 0x57 3b111

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