本节介绍极简设置的软件要求。适用于 Jacinto™ 7 处理器的软件开发套件 (SDK) 用于在测试期间控制和监测此参考设计（如图 4-1 所示）上的以太网 PHY。

需要为适用于 Jacinto™ 7 处理器的 Linux SDK 添加汽车以太网 PHY 驱动程序，才能识别以太网 PHY。请参阅如何将 Linux 驱动程序集成到您的系统中 应用手册。

Jacinto™ 7 SDK v10 的以下代码块中显示了此特定电路板（PHY 配置为 PHY 地址 15）的 Linux 器件树叠加层。有关其他 SDK 版本，请参阅 SDK 文档。

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-cadence.h>
#include "k3-pinctrl.h"
#include "k3-serdes.h"

&{/} {
	aliases {
		ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
	};
};

&cpsw0 {
	status = "okay";
};

&cpsw0_port2 {
	status = "okay";
	phy-handle = <&cpsw9g_phy15>;
	phy-mode = "sgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 2>;
};

&cpsw9g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio0_pins_default>;
	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy15: ethernet-phy@15 {
		reg = <15>;
	};
};

&exp2 {
	qsgmii-line-hog {
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "qsgmii-pwrdn-line";
	};
};

&main_pmx0 {
	mdio0_pins_default: mdio0-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};
};

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz0 {
	status = "okay";
};

&serdes0 {
	status = "okay";

	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
	assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
	#address-cells = <1>;
	#size-cells = <0>;

	serdes0_qsgmii_link: phy@1 {
		reg = <1>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_SGMII>;
		resets = <&serdes_wiz0 2>;
	};
};

除了添加 PHY 驱动程序和调整器件树外，还需要完成以下操作，才能启用 SGMII 接口：

在以下文件中： SDK_Install_Directory/board-support/ti-u-boot-<version>/configs/j721e_evm_a72_defconfig

使用 # 注释掉以下两行代码，如下所示：

# CONFIG_PHY_CADENCE_SIERRA=y 
# CONFIG_PHY_J721E_WIZ=y 

接下来，使用顶层 make 命令来编译 u-boot：

make u-boot

将编译二进制文件 u-boot.img 和 tispl.bin 复制到 SD 卡的引导分区。

sudo cp SDK_Install_Directory/board-support/ti-u-boot-x/build/a72/u-boot.img /media/$USER/boot
sudo cp SDK_Install_Directory/board-support/ti-u-boot-x/build/a72/tispl.bin /media/$USER/boot

使用以下命令更改 r5f0_0-fw 的链接固件：

ln -sfn /usr/lib/firmware/ti-ipc/j721e/ipc_echo_test_mcu2_0_release_strip.xer5f /lib/firmware/j7-main-r5f0_0-fw

电路板上电后，使用以下终端命令确认 PHY 地址 (phy[x]) 和 eth 端口 (eth[y])：

dmesg | grep mdio

davinci_mdio c000f00.mdio: phy[15]: device c000f00.mdio:0f, driver TI DP83TC817CS2.0
am65-cpsw-nuss c000000.ethernet eth1: PHY [c000f00.mdio:0f] driver [TI DP83TC817CS2.0] (irq=POLL)