74ACT11286

Name: 74ACT11286
Brand: TI
SKU: 74ACT11286
Price: 1.631 USD

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具有总线驱动器奇偶校验 I/O 端口的 9 位奇偶校验发生器/校验器

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数据表

document-pdfAcrobat 9-Bit Parity Generator/Checker With Bus Driver Parity I/O Ports 数据表 (Rev. B) (英语)

74ACT11286

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数据表

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Technology family

ACT

Bits (#)

9

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ACT

Bits (#)

9

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (D)

14

51.9 mm² 8.65 x 6

Inputs Are TTL-Voltage Compatible
Generates Either Odd or Even Parity for Nine Data Lines
Cascadable for n-Bits Parity
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)

EPIC is a trademark of Texas Instruments Incorporated.

Inputs Are TTL-Voltage Compatible
Generates Either Odd or Even Parity for Nine Data Lines
Cascadable for n-Bits Parity
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N)

EPIC is a trademark of Texas Instruments Incorporated.

The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.

The control input is implemented specifically to accommodate cascading. When the is low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.

The 74ACT11286 is characterized for operation from -40°C to 85°C.

The 74ACT11286 universal 9-bit parity generator/checker features a local output for parity checking and a bus-driving parity I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.

The control input is implemented specifically to accommodate cascading. When the is low, the parity tree is disabled and the PARITY ERROR output remains at a high logic level, regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A through I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry is designed so that the I/O port remains in the high-impedance state during power up or power down, to prevent bus glitches.

The 74ACT11286 is characterized for operation from -40°C to 85°C.

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