ADC08D1520QML-SP
- Total Ionizing Dose 300 krad(Si)
- Single Event Latch-up 120 MeV-cm2/mg
- Single +1.9V ±0.1V Operation
- Interleave Mode for 2x Sample Rate
- Multiple ADC Synchronization Capability
- Adjustment of Input Full-Scale Range, Offset and Clock Phase Adjustment
- Choice of SDR or DDR output clocking
- 1:1 or 1:2 Selectable Output Demux
- Second DCLK output
- Duty Cycle Corrected Sample Clock
- Test pattern
- Serial Interface for Extended Control
Key Specifications
- Resolution 8 Bits
- Max Conversion Rate 1.5 GSPS (min)
- Code Error Rate 10-18 (typ)
- ENOB at 748 MHz Input 7.2 Bits (typ)
- DNL ±0.15 LSB (typ)
- Power Consumption
- Operating in 1:2 Demux Output 2.0 W (typ)
- Power Down Mode 2.9 mW (typ)
All trademarks are the property of their respective owners.
The ADC08D1520 is an 8–Bit, dual channel, low power, high performance CMOS analog-to-digital converter that builds upon the ADC08D1000 platform. The ADC08D1520 digitizes signals to 8 bits of resolution at sample rates up to 1.7 GSPS. It has expanded features compared to the ADC08D1000, which include a test pattern output for system debug, clock phase adjust, and selectable output demultiplexer modes. Consuming a typical 2.0W in Demultiplex Mode at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.2 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ are at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.
The converter typically consumes less than 2.9 mW in the Power Down Mode and is available in a 128-pin, thermally enhanced, multi-layer ceramic quad package and operates over the Military (-55°C ≤ TA ≤ +125°C) temperature range.
技术文档
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®
借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短米6体育平台手机版_好二三四上市时间并降低开发成本。
在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
CFP (NBC) | 128 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
推荐米6体育平台手机版_好二三四可能包含与 TI 此米6体育平台手机版_好二三四相关的参数、评估模块或参考设计。