CD4075B

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3 通道、3 输入、3V 至 18V 或门

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数据表

document-pdfAcrobat CD4071B, CD4072B, CD4075B TYPES 数据表 (Rev. D) (英语)

CD4075B

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数据表

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米6体育平台手机版_好二三四详情

Technology family

CD4000

Supply voltage (min) (V)

Supply voltage (max) (V)

Number of channels

Inputs per channel

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Supply voltage (min) (V)

Supply voltage (max) (V)

Number of channels

Inputs per channel

IOL (max) (mA)

6.8

IOH (max) (mA)

-6.8

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

181.42 mm² 19.3 x 9.4

SOIC (D)

51.9 mm² 8.65 x 6

SOP (NS)

79.56 mm² 10.2 x 7.8

TSSOP (PW)

32 mm² 5 x 6.4

Medium-Speed Operation - t_PLH, t_PHL = 60 ns (typ.) at V_DD = 10 V
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Standardized, symmetrical output characteristics
Noise margin (full package-temperature range):
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Medium-Speed Operation - t_PLH, t_PHL = 60 ns (typ.) at V_DD = 10 V
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Standardized, symmetrical output characteristics
Noise margin (full package-temperature range):
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

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SN74HCS4075

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具有施密特触发输入的 3 通道、3 输入、2V 至 6V、高速 (12ns) 或门 Shorter average propagation delay (12ns)

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	类型	标题	下载最新的英语版本	日期
*	数据表	CD4071B, CD4072B, CD4075B TYPES 数据表 (Rev. D)		2003年 8月 21日
	选择指南	Logic Guide (Rev. AB)		2017年 6月 12日
	应用手册	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015年 12月 2日
	选择指南	逻辑器件指南 2014 (Rev. AA)	最新英语版本 (Rev.AB)	2014年 11月 17日
	用户指南	LOGIC Pocket Data Book (Rev. B)		2007年 1月 16日
	应用手册	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日
	用户指南	Signal Switch Data Book (Rev. A)		2003年 11月 14日
	应用手册	Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics		2001年 12月 3日