主页 逻辑和电压转换 逻辑门 与非门
主页
逻辑和电压转换
逻辑门
与非门

CD4093B

正在供货

具有施密特触发输入的 4 通道、双输入、3V 至 18V 与非门

立即订购
数据表

CD4093B

正在供货
数据表 立即订购

米6体育平台手机版_好二三四详情

Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Input type Schmitt-Trigger Output type Push-Pull Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125
Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Input type Schmitt-Trigger Output type Push-Pull Features Standard speed (tpd > 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Schmitt-trigger action on each input with no external components
  • Hysteresis voltage typically 0.9 V at VDD = 5 V and 2.3 V at VDD = 10 V
  • Noise immunity greater than 50%
  • No limit on input rise and fall times
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • Wave and pulse shapers
    • High-noise-environment systems
    • Monostable multivibrators
    • Astable multivibrators
    • NAND logic
  • Schmitt-trigger action on each input with no external components
  • Hysteresis voltage typically 0.9 V at VDD = 5 V and 2.3 V at VDD = 10 V
  • Noise immunity greater than 50%
  • No limit on input rise and fall times
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range, 100 nA at 18 V and 25°C
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:
    • Wave and pulse shapers
    • High-noise-environment systems
    • Monostable multivibrators
    • Astable multivibrators
    • NAND logic

CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive- and negative-going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH) (see Fig. 2).

The CD4093B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4093B consists of four Schmitt-trigger circuits. Each circuit functions as a two-input NAND gate with Schmitt-trigger action on both inputs. The gate switches at different points for positive- and negative-going signals. The difference between the positive voltage (VP) and the negative voltage (VN) is defined as hysteresis voltage (VH) (see Fig. 2).

The CD4093B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).
filter 查找其他 与非门
下载 观看带字幕的视频 视频

您可能感兴趣的相似米6体育平台手机版_好二三四

open-in-new 比较替代米6体育平台手机版_好二三四
功能与比较器件相同，且具有相同引脚
SN74LVC00A 正在供货 4 通道、双输入、1.65V 至 3.6V 与非门 Smaller voltage range (1.65V to 5.5V), shorter average propagation delay (5.5ns), higher average drive strength (24mA)

技术文档

star =有关此米6体育平台手机版_好二三四的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 8
类型 标题 下载最新的英语版本 日期
* 数据表 CD4093B Types 数据表 (Rev. D) 2003年 8月 21日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
应用手册 Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑米6体育平台手机版_好二三四通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 旨在支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
TI.com 上无现货
仿真模型

CD4093B PSPICE Model (Rev. A)

SCHM024A.ZIP (7 KB) - PSpice Model
下载
封装 引脚 CAD 符号、封装和 3D 模型
PDIP (N) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频