CD74HCT191

Name: CD74HCT191
Brand: TI
SKU: CD74HCT191
Price: 0.311 USD

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高速 CMOS 逻辑可预设的同步 4 位二进制加/减计数器

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数据表

document-pdfAcrobat CD54HC190, CD74HC190, CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 数据表 (Rev. E) (英语)

CD74HCT191

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数据表

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Function

Counter

Bits (#)

4

Technology family

HCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Presettable

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Function

Counter

Bits (#)

4

Technology family

HCT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

Push-Pull

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Presettable

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

2-V to 6-V V_CC Operation (’HC190,191)
4.5-V to 5.5-V V_CC Operation (’HCT191)
Wide Operating Temperature Range of –55 to 125°C
Synchronous Counting and Asynchronous Loading
Two Outputs for n-Bit Cascading
Look-Ahead Carry for High-Speed Counting
Balanced Propagation Delay and Transition Times
Standard Outputs Drive Up To 15 LS-TTL Loads
Significant Power Reduction Compared to LS-TTL Logic ICs

2-V to 6-V V_CC Operation (’HC190,191)
4.5-V to 5.5-V V_CC Operation (’HCT191)
Wide Operating Temperature Range of –55 to 125°C
Synchronous Counting and Asynchronous Loading
Two Outputs for n-Bit Cascading
Look-Ahead Carry for High-Speed Counting
Balanced Propagation Delay and Transition Times
Standard Outputs Drive Up To 15 LS-TTL Loads
Significant Power Reduction Compared to LS-TTL Logic ICs

The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.

Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.

When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).

The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.

Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.

When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).

If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).

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