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数字多路信号分离器和解码器

CD74HCT237

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具有地址锁存器的高速 CMOS 逻辑 3 线至 8 线解码器/多路信号分离器

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数据表

CD74HCT237

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数据表 立即订购

米6体育平台手机版_好二三四详情

Technology family HCT Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Catalog Supply current (max) (µA) 160
Technology family HCT Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Catalog Supply current (max) (µA) 160
PDIP (N) 16 181.42 mm² 19.3 x 9.4
  • Select One of Eight Data Outputs
    • Active Low for CD74HC137 and CD74HCT137
    • Active High for ’HC237 and CD74HCT237
  • I/O Port or Memory Selector
  • Two Enable Inputs to Simplify Cascading
  • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25°C (CD74HC237)
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . 10 LSTTL Loads
    • Bus Driver Outputs. . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor
  • Select One of Eight Data Outputs
    • Active Low for CD74HC137 and CD74HCT137
    • Active High for ’HC237 and CD74HCT237
  • I/O Port or Memory Selector
  • Two Enable Inputs to Simplify Cascading
  • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25°C (CD74HC237)
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . 10 LSTTL Loads
    • Bus Driver Outputs. . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.

Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a "Low"; in the ’HC237 and CD74HCT237 the selected output is a "High".

The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.

Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a "Low"; in the ’HC237 and CD74HCT237 the selected output is a "High".
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SN74HCT138 正在供货 3 线至 8 线解码器/多路信号分离器 Voltage range (4.5V to 5.5V), average drive strength (4mA), average propagation delay (22ns)

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类型 标题 下载最新的英语版本 日期
* 数据表 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 数据表 (Rev. F) 2003年 10月 13日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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