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CD74HCT356

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具有三态输出的高速 CMOS 逻辑 8 输入多路复用器/寄存器

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数据表

CD74HCT356

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数据表 立即订购

米6体育平台手机版_好二三四详情

Technology family HCT Function Digital Multiplexer Configuration 8:1 Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Catalog
Technology family HCT Function Digital Multiplexer Configuration 8:1 Number of channels 1 Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 20 228.702 mm² 24.33 x 9.4
  • Edge-Triggered Data Flip-Flops
    • Transparent Select Latches
  • Buffered Inputs
  • 3-State Complementary Outputs
  • Bus Line Driving Capability
  • Typical Propagation Delay: VCC= 5V, CL = 15pF, TA = 25°C
    • Clock to Output = 22ns
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il 1µA at VOL, VOH
  • Edge-Triggered Data Flip-Flops
    • Transparent Select Latches
  • Buffered Inputs
  • 3-State Complementary Outputs
  • Bus Line Driving Capability
  • Typical Propagation Delay: VCC= 5V, CL = 15pF, TA = 25°C
    • Clock to Output = 22ns
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
  • CMOS Input Compatibility, Il 1µA at VOL, VOH

The CD74HCT356 consists of data selectors/multiplexers that select one of eight sources. The data select bits (S0, S1, and S2) are stored in transparent latches that are enabled by a low latch enable input (LE\).

The data is stored in edge-triggered flip-flops that are triggered by a low-to-high clock transition.

In both types the 3-state outputs are controlled by three output-enable inputs (OE1\, OE2\, and OE3).

The CD74HCT356 consists of data selectors/multiplexers that select one of eight sources. The data select bits (S0, S1, and S2) are stored in transparent latches that are enabled by a low latch enable input (LE\).

The data is stored in edge-triggered flip-flops that are triggered by a low-to-high clock transition.

In both types the 3-state outputs are controlled by three output-enable inputs (OE1\, OE2\, and OE3).
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CD74HCT251 正在供货 具有三态输出的高速 CMOS 逻辑 8 输入多路复用器 Voltage range (4.5V to 5.5V), average drive strength (4mA), average propagation delay (22ns)

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类型 标题 下载最新的英语版本 日期
* 数据表 CD74HCT356 数据表 (Rev. A) 2003年 5月 8日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训