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时钟缓冲器

CDCLVD110

不推荐用于新设计

具有最小时钟分配偏移且频率高达 900MHz 的 1:10 LVDS 时钟缓冲器

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CDCLVD110 不推荐用于新设计
该米6体育平台手机版_好二三四会持续为现有客户提供。新设计应考虑替代米6体育平台手机版_好二三四。
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CDCLVD110A 正在供货 通过超小偏斜实现时钟分配且频率高达 1100MHz 的 1:10 LVDS 时钟缓冲器 Offers better jitter performance

CDCLVD110

不推荐用于新设计
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米6体育平台手机版_好二三四详情

Function Differential Core supply voltage (V) 2.5 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVDS
Function Differential Core supply voltage (V) 2.5 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVDS
LQFP (VF) 32 81 mm² 9 x 9
  • Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
  • Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
  • VCC range 2.5 V ±5%
  • Typical Signaling Rate Capability of Up to 1.1 GHz
  • Configurable Register (SI/CK) Individually Enables Disables Outputs,
    Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
  • Full Rail-to-Rail Common-Mode Input Range
  • Receiver Input Threshold ±100 mV
  • Available in 32-Pin LQFP Package
  • Fail-Safe I/O-Pins for VDD = 0 V (Power Down)
  • Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
  • Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
  • VCC range 2.5 V ±5%
  • Typical Signaling Rate Capability of Up to 1.1 GHz
  • Configurable Register (SI/CK) Individually Enables Disables Outputs,
    Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
  • Full Rail-to-Rail Common-Mode Input Range
  • Receiver Input Threshold ±100 mV
  • Available in 32-Pin LQFP Package
  • Fail-Safe I/O-Pins for VDD = 0 V (Power Down)

The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50- transmission lines.

When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.

The CDCLVD110 is characterized for operation from -40°C to 85°C.

Not Recommended for New Designs. Use CDCLVD110A as a Replacement.

The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50- transmission lines.

When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.

The CDCLVD110 is characterized for operation from -40°C to 85°C.

Not Recommended for New Designs. Use CDCLVD110A as a Replacement.
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类型 标题 下载最新的英语版本 日期
* 数据表 Programmable Low-Voltage 1:10 LVDS Clock Driver 数据表 (Rev. C) 2008年 1月 14日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点