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CDCVF2310

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适用于通用应用且支持高达 105°C 温度的高性能 1:10 时钟缓冲器

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CDCVF2310

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米6体育平台手机版_好二三四详情

Function Single-ended Additive RMS jitter (typ) (fs) 45 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
Function Single-ended Additive RMS jitter (typ) (fs) 45 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • High-Performance 1:10 Clock Driver
  • Operates up to 200 MHz at VDD 3.3 V
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range: 2.3 V to 3.6 V
  • Operating Temperature Range –40°C to 105°C
  • Supports 105ºC Ambient Temperature (see
    Thermal Considerations)
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five
    Outputs
  • 25-Ω On-Chip Series Damping Resistors
  • Packaged in 24-Pin TSSOP
  • High-Performance 1:10 Clock Driver
  • Operates up to 200 MHz at VDD 3.3 V
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range: 2.3 V to 3.6 V
  • Operating Temperature Range –40°C to 105°C
  • Supports 105ºC Ambient Temperature (see
    Thermal Considerations)
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five
    Outputs
  • 25-Ω On-Chip Series Damping Resistors
  • Packaged in 24-Pin TSSOP

The CDCVF2310 device is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF2310 is characterized for operation from –40°C to 85°C.

The CDCVF2310 device is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF2310 is characterized for operation from –40°C to 85°C.
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类型 标题 下载最新的英语版本 日期
* 数据表 CDCVF2310 2.5-V to 3.3-V High-Performance Clock Buffer 数据表 (Rev. D) PDF | HTML 2015年 10月 30日
应用手册 Using TI's CDCVF2310 and CDCVF25081 with TLK1501 Serial Transceiver 2003年 5月 14日

设计和开发

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仿真模型

CDCVF2310 IBIS Model (Rev. C)

SCAC026C.ZIP (33 KB) - IBIS Model
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包含信息：
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  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
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