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DS25BR440

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具有发送预加重和接收均衡功能的 3.125Gbps 四通道 LVDS 缓冲器

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数据表

DS25BR440

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数据表 立即订购

米6体育平台手机版_好二三四详情

Function Buffer, Equalizer, Redriver, Repeater Protocols CML, LVDS, LVPECL Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 3125 Input signal CML, LVCMOS, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer, Equalizer, Redriver, Repeater Protocols CML, LVDS, LVPECL Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 3125 Input signal CML, LVCMOS, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RTA) 40 36 mm² 6 x 6
  • DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
  • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter
  • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to LVDS, CML and LVPECL Drivers
  • LOS Circuitry Detects Open Inputs Fault
  • Integrated 100Ω Input and Output Terminations
  • 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
  • Small 6 mm x 6 mm WQFN-40 Space Saving Package

All trademarks are the property of their respective owners.

  • DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
  • Pin Selectable Transmit Pre-Emphasis and Receive Equalization Eliminate Data Dependant Jitter
  • Wide Input Common Mode Voltage Range Allows DC-Coupled Interface to LVDS, CML and LVPECL Drivers
  • LOS Circuitry Detects Open Inputs Fault
  • Integrated 100Ω Input and Output Terminations
  • 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
  • Small 6 mm x 6 mm WQFN-40 Space Saving Package

All trademarks are the property of their respective owners.

The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR440 features two levels of transmit pre-emphasis (PE) and two levels of receive equalization (EQ). Both of these features compensate for interconnect losses and ultimately maximize noise margin. A loss-of-signal (LOS) circuit monitors each input channel and a unique LOS pin is asserted when no signal is detected at that input.

Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device return losses, reduce component count and further minimize board space.

The DS25BR440 is a 3.125 Gbps Quad LVDS buffer optimized for high-speed signal routing and repeating over lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR440 features two levels of transmit pre-emphasis (PE) and two levels of receive equalization (EQ). Both of these features compensate for interconnect losses and ultimately maximize noise margin. A loss-of-signal (LOS) circuit monitors each input channel and a unique LOS pin is asserted when no signal is detected at that input.

Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device return losses, reduce component count and further minimize board space.
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类型 标题 下载最新的英语版本 日期
* 数据表 3.125 Gbps Quad LVDS Buffer w/ Transmit Pre-Emphasis and Receive Equalization 数据表 (Rev. B) 2013年 3月 4日
设计指南 适用于 Xilinx FPGA 的模拟器件 解决方案指南 2012年 4月 24日

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