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SN54AHC123A

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SN54AHC123A

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米6体育平台手机版_好二三四详情

Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Technology family AHC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 40 IOL (max) (mA) 8 IOH (max) (mA) -8 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Retriggerable Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Technology family AHC Input type Schmitt-Trigger Output type Push-Pull Supply current (µA) 40 IOL (max) (mA) 8 IOH (max) (mA) -8 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Retriggerable Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Operating Range 2-V to 5.5-V VCC
  • Schmitt-Trigger Circuitry On A\, B, and CLR\ Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset On Outputs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Operating Range 2-V to 5.5-V VCC
  • Schmitt-Trigger Circuitry On A\, B, and CLR\ Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset On Outputs
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The ’AHC123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A\ input is low, and the B input goes high. In the second method, the B input is high, and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR)\ input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A\) or high-level-active (B) input. Pulse duration can be reduced by taking CLR\ low. CLR\ input can be used to override A\ or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’AHC123A is shown in Figure 10. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 6.

During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

For additional application information on multivibrators, see the application report Designing With the SN74AHC123A and SN74AHCT123A, literature number SCLA014.

The ’AHC123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A\ input is low, and the B input goes high. In the second method, the B input is high, and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR)\ input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A\) or high-level-active (B) input. Pulse duration can be reduced by taking CLR\ low. CLR\ input can be used to override A\ or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’AHC123A is shown in Figure 10. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 6.

During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

For additional application information on multivibrators, see the application report Designing With the SN74AHC123A and SN74AHCT123A, literature number SCLA014.
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类型 标题 下载最新的英语版本 日期
* 数据表 SN54AHC123A, SN74AHC123A 数据表 (Rev. H) 2005年 10月 21日
* SMD SN54AHC123A SMD 5962-98608 2016年 6月 21日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
应用手册 使用 SN74LVC1G123 单稳多谐振荡器进行设计 (Rev. A) PDF | HTML 英语版 (Rev.A) PDF | HTML 2021年 7月 20日
选择指南 Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 How to Select Little Logic (Rev. A) 2016年 7月 26日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
选择指南 小尺寸逻辑器件指南 (Rev. E) 最新英语版本 (Rev.G) 2012年 7月 16日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 选择正确的电平转换解决方案 (Rev. A) 英语版 (Rev.A) 2006年 3月 23日
米6体育平台手机版_好二三四概述 Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 2002年 12月 2日
应用手册 Texas Instruments Little Logic Application Report 2002年 11月 1日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
设计指南 AHC/AHCT Designer's Guide February 2000 (Rev. D) 2000年 2月 24日
应用手册 Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
米6体育平台手机版_好二三四概述 Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 1998年 4月 1日
应用手册 Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
应用手册 Live Insertion 1996年 10月 1日

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封装 引脚 CAD 符号、封装和 3D 模型
CDIP (J) 16 Ultra Librarian
CFP (W) 16 Ultra Librarian
LCCC (FK) 20 Ultra Librarian
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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 封装厂地点

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