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D 型触发器

SN54LS379

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具有使能端的四通道 D 类触发器

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数据表

SN54LS379

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数据表 立即订购

米6体育平台手机版_好二三四详情

Number of channels 4 Technology family LS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type TTL Clock frequency (max) (MHz) 40 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 15000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 4 Technology family LS Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type Bipolar Output type TTL Clock frequency (max) (MHz) 40 IOL (max) (mA) 8 IOH (max) (mA) -0.4 Supply current (max) (µA) 15000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • 'LS377 and 'LS378 Contain Eight and Six Flip-Flops, Respectively, with Single-Rail Outputs
  • 'LS379 Contains Four Flip-Flops with Double-Rail Outputs
  • Individual Data Input to Each Flip-Flop
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

 
  • 'LS377 and 'LS378 Contain Eight and Six Flip-Flops, Respectively, with Single-Rail Outputs
  • 'LS379 Contains Four Flip-Flops with Double-Rail Outputs
  • Individual Data Input to Each Flip-Flop
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators

 

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input.

These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.

 

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G\ input.

These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.

 
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* 数据表 Octal, Hex, And Quad D-Type Flip-Flops With Enable 数据表 1988年 3月 1日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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