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SN74AHC8541

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SN74AHC8541

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数据表

SN74AHC8541

正在供货
数据表 立即订购

米6体育平台手机版_好二三四详情

Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 8 Inputs per channel 1 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 110 Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 8 Inputs per channel 1 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 110 Rating Catalog Operating temperature range (°C) -40 to 85
PDIP (N) 20 228.702 mm² 24.33 x 9.4
  • Operating Range of 2 V to 5.5 V VCC
  • 8-Bit Inverting/Non-Inverting Outputs
  • 20-Pin Thin Shrink Small-Outline Package
    [TSSOP (PW)] and 20-Pin Plastic Dual-In-Line
    Package [PDIP (N)]
  • Operating Range of 2 V to 5.5 V VCC
  • 8-Bit Inverting/Non-Inverting Outputs
  • 20-Pin Thin Shrink Small-Outline Package
    [TSSOP (PW)] and 20-Pin Plastic Dual-In-Line
    Package [PDIP (N)]

The SN74AHC8541 8-bit inverting/non-inverting buffers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

All outputs are in the high-impedance state (disabled) when the output-enable (OE) input is high. When OE is low, the respective gate passes the data from the D input to its Y output.

The T/C input selects inverting or non-inverting data transfer. When the T/C input is high, it provides non-inverting buffers. When the T/C input is low, it provides inverting buffers when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AHC8541 8-bit inverting/non-inverting buffers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

All outputs are in the high-impedance state (disabled) when the output-enable (OE) input is high. When OE is low, the respective gate passes the data from the D input to its Y output.

The T/C input selects inverting or non-inverting data transfer. When the T/C input is high, it provides non-inverting buffers. When the T/C input is low, it provides inverting buffers when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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SN74AHC541 正在供货 具有三态输出的 8 通道、2V 至 5.5V 缓冲器 Voltage range (2V to 5.5V), average drive strength (9mA), average propagation delay (12ns)

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类型 标题 下载最新的英语版本 日期
* 数据表 SN74AHC8541 8-BIT INVERTING/NONINVERTING SCHMITT-TRIGGER BUFFERS W/3-STATE OUT 数据表 2009年 4月 8日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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