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固定方向电压转换器

SN74AUP1T14

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低功耗、1.8/2.5/3.3V 输入、3.3V CMOS 输出、单路施密特触发反向器闸

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SN74AUP1T14

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米6体育平台手机版_好二三四详情

Technology family AUP1T Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 1.35 High input voltage (max) (V) 3.6 Vout (min) (V) 206002 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) -4 Supply current (max) (µA) 3.6 Features 4.2 Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP1T Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 1.35 High input voltage (max) (V) 3.6 Vout (min) (V) 206002 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -4 IOL (max) (mA) -4 Supply current (max) (µA) 3.6 Features 4.2 Input type Schmitt-Trigger Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and Provide
    Better Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 µA
  • Very Low Dynamic Power Consumption:
    0.9 µA
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)
    2 × 2.1 × 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Single-Supply Voltage Translator
  • Output Level Up to Supply VCC CMOS Level
    • 1.8 V to 3.3 V (at VCC = 3.3 V)
    • 2.5 V to 3.3 V (at VCC = 3.3 V)
    • 1.8 V to 2.5 V (at VCC = 2.5 V)
    • 3.3 V to 2.5 V (at VCC = 2.5 V
  • Schmitt-Trigger Inputs Reject Input Noise and Provide
    Better Output Signal Integrity
  • Ioff Supports Partial Power Down (VCC = 0 V)
  • Very Low Static Power Consumption:
    0.1 µA
  • Very Low Dynamic Power Consumption:
    0.9 µA
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Pb-Free Packages Available: SC-70 (DCK)
    2 × 2.1 × 0.65 mm (Height 1.1 mm)
  • More Gate Options Available at www.ti.com/littlelogic
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

The SN74AUP1T14 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T14 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

The SN74AUP1T14 performs the Boolean function Y = A with designation for logic-level translation applications with output referenced to supply VCC.

AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).

The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.

Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.

Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.

The SN74AUP1T14 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
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SN74LXC1T14 正在供货 单通道固定方向反相 1.1V 至 5.5V 电压电平转换器 5 V version of 1 bit translating inverter gate with Schmitt trigger inputs 

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类型 标题 下载最新的英语版本 日期
* 数据表 Low Power, 1.8/2.5/3.3-V In, 3.3-V CMOS Out Single Schmitt-Trigger Inverter Gate 数据表 2010年 4月 16日
应用手册 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
应用手册 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
应用手册 了解 CMOS 输出缓冲器中的瞬态驱动强度与直流驱动强度 PDF | HTML 最新英语版本 (Rev.A) PDF | HTML 2024年 5月 15日
应用简报 了解施密特触发器 (Rev. A) PDF | HTML 英语版 (Rev.A) PDF | HTML 2022年 12月 1日
选择指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

5-8-LOGIC-EVM — 支持 5 至 8 引脚 DCK、DCT、DCU、DRL 和 DBV 封装的通用逻辑评估模块

灵活的 EVM 设计用于支持具有 5 至 8 引脚数且采用 DCK、DCT、DCU、DRL 或 DBV 封装的任何器件。
用户指南: PDF
TI.com 上无现货
参考设计

TIDA-00684 — 高带宽任意波形发生器参考设计：直流或交流耦合，高压输出

TIDA-00684 参考设计开发了一款四通道 TSW3080 评估模块 (EVM)，展示了如何使用采用 DAC38J84 的有源放大器接口来演示任意波形发生器前端。DAC38J84 能够以 16 位分辨率和最高可达 2.5GSPS 的更新速率提供四个 DAC 通道。THS3217 可提供宽带差动到单端输出。THS3095 可提供高达 26Vpp 的高动态范围输出。LMH5401 可提供频带较宽的差动输出。所有这些路径都提供了直流耦合接口，能够以高性能级别驱动 50Ω 负载。此参考设计还包括用于对比目的的参考变压器路径。
设计指南: PDF
原理图: PDF
封装 引脚 CAD 符号、封装和 3D 模型
SOT-SC70 (DCK) 5 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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