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方向控制型电压转换器

SN74AVC2T245

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具有可配置电压转换和三态输出的双位 2-DIR 引脚双电源总线收发器

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SN74AXC2T245 正在供货 具有可配置电压转换和三态输出的双位 2 DIR 引脚双电源总线收发器 Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC2T245

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米6体育平台手机版_好二三四详情

Technology family AVC Applications JTAG Bits (#) 2 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Applications JTAG Bits (#) 2 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
UQFN (RSW) 10 2.52 mm² 1.8 x 1.4
  • Each Channel Has Independent Direction Control
  • Control Inputs VIH/VIL Levels Are Referenced to
    VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.2 V to
    3.6 V Power-Supply Range
  • I/Os Are 4.6 V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • VCC Isolation Feature - If Either VCC Input is at
    GND, Both Ports are in High-Impedance State
  • Typical Data Rates
    • 500 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (<1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000 V Human-Body Model (A114-A)
    • 200 V Machine Model (A115-A)
    • 1500 V Charged-Device Model (C101)
  • Each Channel Has Independent Direction Control
  • Control Inputs VIH/VIL Levels Are Referenced to
    VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.2 V to
    3.6 V Power-Supply Range
  • I/Os Are 4.6 V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • VCC Isolation Feature - If Either VCC Input is at
    GND, Both Ports are in High-Impedance State
  • Typical Data Rates
    • 500 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (<1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000 V Human-Body Model (A114-A)
    • 200 V Machine Model (A115-A)
    • 1500 V Charged-Device Model (C101)

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC2T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC2T245 control pins (DIR1, DIR2, and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC2T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC2T245 control pins (DIR1, DIR2, and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 SN74AVC2T245 Dual-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting / Voltage Translation and Tri-State Outputs 数据表 (Rev. D) PDF | HTML 2016年 2月 22日
应用手册 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
应用手册 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
应用手册 了解 CMOS 输出缓冲器中的瞬态驱动强度与直流驱动强度 PDF | HTML 最新英语版本 (Rev.A) PDF | HTML 2024年 5月 15日
选择指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
EVM 用户指南 SN74AXC2T-SMALLPKGEVM Evaluation module user's guide 2019年 6月 4日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
应用手册 Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 选择正确的电平转换解决方案 (Rev. A) 英语版 (Rev.A) 2006年 3月 23日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
更多文献资料 LCD Module Interface Application Clip 2003年 5月 9日
用户指南 AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
更多文献资料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
应用手册 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
应用手册 Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
应用手册 AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

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用户指南: PDF
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无论是 Linux 还是 TI-RTOS 操作系统，处理器 SDK 均支持此 EVM，而且此 EVM 采用 USB、PCIe 和千兆位以太网等主要外设。  (...)

用户指南: PDF
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仿真模型

HSPICE Model for SN74AVC2T245

SCEM533.ZIP (102 KB) - HSpice Model
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仿真模型

SN74AVC2T245 IBIS Model

SCEM532.ZIP (64 KB) - IBIS Model
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参考设计

TIDEP0050 — EnDat 2.2 系统参考设计

此参考设计基于 HEIDENHAIN EnDat 2.2 标准针对位置或旋转编码器实现了 EnDat 2.2 主协议栈和硬件接口。此设计由 EnDat 2.2 主协议栈、使用 RS-485 收发器的半双工通信，以及在 Sitara AM437x 工业开发工具包上实现的线路终端组成。此设计经过充分测试，符合 HEIDENHAIN EnDat 2.2 标准。除了 EnDat 位置反馈之外，AM437x IDK 还能够支持工业通信和电机驱动，如 AM437x 单芯片电机控制设计指南中所述。
设计指南: PDF
原理图: PDF
参考设计

TIDA-00403 — 采用 TLV320AIC3268 miniDSP 编解码器的超声波测距参考设计

TIDA-00403 参考设计使用针对超声测距解决方案的现成的 EVM，该解决方案使用 TLV320AIC3268 miniDSP 内的算法。通过将该设计与 TI 的 PurePath Studio 设计套件结合使用，只需点击鼠标即可设计出一个用户可配置的稳健的超声测距系统。用户可以修改超声波脉冲生成特性以及检测算法以适合工业和测量应用中的特定使用情况，从而让用户能解决其他固定功能传感器的限制，同时增加测量的可靠性。TLV320AIC3268 上的两个 GPIO 被自动触发，表明已发出并接收到超声波脉冲。通过利用主机 MCU 监测这些 GPIO 可以提取出飞行时间。
设计指南: PDF
原理图: PDF
封装 引脚 CAD 符号、封装和 3D 模型
UQFN (RSW) 10 Ultra Librarian
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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