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SN74F657

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具有奇偶校验发生器/校验器和三态输出的八路收发器

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SN74F657

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米6体育平台手机版_好二三四详情

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -12 Input type TTL Output type TTL Features Very high speed (tpd 5-10ns) Technology family F Rating Catalog Operating temperature range (°C) 0 to 70
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -12 Input type TTL Output type TTL Features Very high speed (tpd 5-10ns) Technology family F Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Combines ´F245 and ´F280B Functions in One Package
  • High-Impedance N-P-N Inputs for Reduced Loading (70 uA in Low and High States)
  • High Output Drive and Light Bus Loading
  • 3-State B Outputs Sink 64 mA and Source 15 mA
  • Input Diodes for Termination Effects
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 
  • Combines ´F245 and ´F280B Functions in One Package
  • High-Impedance N-P-N Inputs for Reduced Loading (70 uA in Low and High States)
  • High Output Drive and Light Bus Loading
  • 3-State B Outputs Sink 64 mA and Source 15 mA
  • Input Diodes for Termination Effects
  • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

 

The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.

The transmit/receive (T/R\) input determines the direction of the data flow through the bidirectional transceivers. When T/R\ is high, data is transmitted from the A port to the B port. When T/R\ is low, data is received at the A port from the B port.

When the output enable () input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN\ input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R\ high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R\ low), PARITY is an input.

When transmitting (T/R\ high), the parity select (ODD/EVEN\) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN\ and the number of high bits on A port. When ODD/EVEN\ is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R\ low), the B port is polled to determine the number of high bits. If ODD/EVEN\ is low (for even parity) and the number of highs on B port is:

  1. 1. Odd and the PARITY input is high, then ERR\ will be high signifying no error.
  2. 2. Even and the PARITY input is high, then ERR\ will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.

 

 

The SN74F657 contains eight noninverting buffers with 3-state outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a specified current sinking capability of 24 mA at the A port and 64 mA at the B port.

The transmit/receive (T/R\) input determines the direction of the data flow through the bidirectional transceivers. When T/R\ is high, data is transmitted from the A port to the B port. When T/R\ is low, data is received at the A port from the B port.

When the output enable () input is high, both the A and B ports are placed in a high-impedance state (disabled). The ODD/EVEN\ input allows the user to select between odd or even parity systems. When transmitting from A port to B port (T/R\ high), PARITY is an output from the generator/checker. When receiving from B port to A port (T/R\ low), PARITY is an input.

When transmitting (T/R\ high), the parity select (ODD/EVEN\) input is made high or low as appropriate. The A port is then polled to determine the number of high bits.The PARITY output goes to the logic state determined by ODD/EVEN\ and the number of high bits on A port. When ODD/EVEN\ is low (for even parity) and the number of high bits on A port is odd, the PARITY will be high, transmitting even parity. If the number of high bits on A port is even, the PARITY will be low, keeping even parity.

When in the receive mode (T/R\ low), the B port is polled to determine the number of high bits. If ODD/EVEN\ is low (for even parity) and the number of highs on B port is:

  1. 1. Odd and the PARITY input is high, then ERR\ will be high signifying no error.
  2. 2. Even and the PARITY input is high, then ERR\ will be low indicating an error.

The SN74F657 is characterized for operation from 0°C to 70°C.

 

 
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类型 标题 下载最新的英语版本 日期
* 数据表 Octal Transceiver With Parity Generator/Checker And 3-State Outputs 数据表 (Rev. A) 1993年 10月 1日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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