主页 逻辑和电压转换 触发器、锁存器和寄存器 D 型触发器
主页
逻辑和电压转换
触发器、锁存器和寄存器
D 型触发器

SN74LV374AT

正在供货

SN74LV374AT

立即订购
数据表

SN74LV374AT

正在供货
数据表 立即订购

米6体育平台手机版_好二三四详情

Number of channels 8 Technology family LV-AT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 50 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 8 Technology family LV-AT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 16 IOH (max) (mA) -16 Supply current (max) (µA) 50 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V VCC Operation
  • Typical tpd of 4.9 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V
    at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V
    at VCC = 5 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Inputs Are TTL-Voltage Compatible
  • 4.5-V to 5.5-V VCC Operation
  • Typical tpd of 4.9 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V
    at VCC = 5 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V
    at VCC = 5 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
filter 查找其他 D 型触发器
下载

您可能感兴趣的相似米6体育平台手机版_好二三四

open-in-new 比较替代米6体育平台手机版_好二三四
功能优于所比较器件的普遍直接替代米6体育平台手机版_好二三四
SN74AHCT374 正在供货 具有三态输出的八路 D 类边沿触发器 Larger voltage range (2V to 5.5V), shorter average propagation delay (9ns)

技术文档

star =有关此米6体育平台手机版_好二三四的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 1
类型 标题 下载最新的英语版本 日期
* 数据表 OCTAL EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS 数据表 2010年 6月 16日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频