SN74LV4T32-EP
- Wide operating range of 1.8 V to 5.5 V
-
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
- 1.2 V to 1.8 V
- 1.5 V to 2.5 V
- 1.8 V to 3.3 V
- 3.3 V to 5.0 V
- Down translation:
- 5.0 V, 3.3 V, 2.5 V to 1.8 V
- 5.0 V, 3.3 V to 2.5 V
- 5.0 V to 3.3 V
- Up translation:
- 5.5-V tolerant input pins
- Supports standard pinouts
- Up to 150Mbps with 5-V or 3.3-V V CC
- Latch-up performance exceeds 250 mA per JESD 17
- Supports defense, aerospace, and medical applications:
- Controlled baseline
- One assembly and test site
- One fabrication site
- Extended product life cycle
- Product traceability
The SN74LV4T32-EP contains four independent 2-input OR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | SN74LV4T32-EPQuadruple 2-Input Positive-OR GatesWith Integrated Translation 数据表 | PDF | HTML | 2023年 11月 15日 | ||
* | 辐射与可靠性报告 | SN74LV4T32-EP Enhanced Product Qualification and Reliability Report | PDF | HTML | 2023年 11月 22日 |
设计和开发
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封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
TSSOP (PW) | 14 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点