SN74LV8153
- Single-Wire Serial Data Input
- Compatible With UART Serial-Data Format
- Up to Eight Devices (64-Bit Parallel) Can Share the Same Bus by Using Different Combinations of A0, A1, A2
- Up to 40 mA Current Drive in Open-Collector Mode for Driving LEDs
- Outputs Can be Configured as Open-Collector or Push-Pull
- Internal Oscillator and Counter for Automatic Data-Rate Detection
- Output Levels Are Referenced to VCC2 and Can Be Configured From 3 V to 12 V
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)
The SN74LV8153 is a serial-to-parallel data converter. It accepts serial input data and outputs 8-bit parallel data.
The automatic data-rate detection feature of the SN74LV8153 eliminates the need for an external oscillator and helps with cost and board real-estate savings.
The OUTSEL pin is used to choose between open collector and push-pull outputs. The open-collector option is suitable when this device is used in applications such as LED interface, where high drive current is required. SOUT is the output that acknowledges reception of the serial data.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC1 through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | SN74LV8153 数据表 | 2003年 12月 17日 | |||
应用手册 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022年 12月 15日 |
设计和开发
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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑米6体育平台手机版_好二三四通用评估模块
14-24-LOGIC-EVM 评估模块 (EVM) 旨在支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。
封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
PDIP (N) | 20 | Ultra Librarian |
TSSOP (PW) | 20 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点