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SN74LV86A

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4 通道、2 输入、2V 至 5.5V XOR（异或）门

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SN74LV86A

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米6体育平台手机版_好二三四详情

Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 12 Input type Standard CMOS IOH (max) (mA) -12 Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 12 Input type Standard CMOS IOH (max) (mA) -12 Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 8 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V
    at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V
    at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Latch-Up Performance Exceeds 250 mA per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 8 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V
    at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V
    at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All Ports
  • Latch-Up Performance Exceeds 250 mA per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The ’LV86A devices are quadruple 2-input exclusive-OR gates designed for 2-V to 5.5-V VCC operation.

These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.

The ’LV86A devices are quadruple 2-input exclusive-OR gates designed for 2-V to 5.5-V VCC operation.

These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output.
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类型 标题 下载最新的英语版本 日期
* 数据表 SNx4LV86A Quadruple 2-Input Exclusive-OR Gates 数据表 (Rev. G) PDF | HTML 2015年 2月 11日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑米6体育平台手机版_好二三四通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 旨在支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
TI.com 上无现货
仿真模型

SN74LV86A Behavioral SPICE Model

SCLM176.ZIP (7 KB) - PSpice Model
下载
仿真模型

SN74LV86A IBIS Model

SCEM124.ZIP (16 KB) - IBIS Model
下载
封装 引脚 CAD 符号、封装和 3D 模型
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

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