SN74LVC8T245-EP

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具有可配置电压转换和三态输出的 8 位双电源总线收发器(增强型米6体育平台手机版_好二三四)

米6体育平台手机版_好二三四详情

Technology family LVC Applications GPIO Bits (#) 8 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 25 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family LVC Applications GPIO Bits (#) 8 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 25 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4 VQFN (RHL) 24 19.25 mm² 5.5 x 3.5
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Are in the High-Impedance State
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Are in the High-Impedance State
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245-EP is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.

The SN74LVC8T245-EP is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC8T245-EP is designed so that the control pins (DIR and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245-EP is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.

The SN74LVC8T245-EP is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC8T245-EP is designed so that the control pins (DIR and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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类型 标题 下载最新的英语版本 日期
* 数据表 SN74LVC8T245-EP 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs 数据表 (Rev. A) PDF | HTML 2017年 3月 2日
* 辐射与可靠性报告 CLVC1G126IDCKREP Reliability Report 2018年 1月 25日
* VID SN74LVC8T245-EP VID V6209615 2016年 6月 21日
* 辐射与可靠性报告 SN74LVC8T245MPWREP Reliability Report 2015年 2月 6日
* 辐射与可靠性报告 SN74LVC8T245MPWREP Reliability Report 2011年 8月 31日
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应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
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选择指南 小尺寸逻辑器件指南 (Rev. E) 最新英语版本 (Rev.G) 2012年 7月 16日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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设计和开发

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评估板

14-24-NL-LOGIC-EVM — 采用 14 引脚至 24 引脚无引线封装的逻辑米6体育平台手机版_好二三四通用评估模块

14-24-EVM 是一款灵活的评估模块 (EVM),旨在支持具有 14 引脚至 24 引脚 BQA、BQB、RGY、RSV、RJW 或 RHL 封装的任何逻辑或转换器件。

用户指南: PDF | HTML
英语版 (Rev.A): PDF | HTML
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仿真模型

SN74LVC8T245 IBIS Model

SCEM494.ZIP (56 KB) - IBIS Model
封装 引脚 CAD 符号、封装和 3D 模型
SOIC (DW) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
VQFN (RHL) 24 Ultra Librarian

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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