主页 逻辑和电压转换 电压转换器和电平转换器 应用特定的电压转换器
主页
逻辑和电压转换
电压转换器和电平转换器
应用特定的电压转换器

SN74LVCE161284

正在供货

具有无误差上电功能的 19 位 IEEE 1284 转换收发器

立即订购
数据表

SN74LVCE161284

正在供货
数据表 立即订购

米6体育平台手机版_好二三四详情

Technology family LVC Applications IEEE1284 Rating Catalog Operating temperature range (°C) 0 to 70
Technology family LVC Applications IEEE1284 Rating Catalog Operating temperature range (°C) 0 to 70
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Auto-Power-Up Feature Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at A9–A13 Pins
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection
    • ±4 kV - Human-Body Model
    • ±8 kV - IEC 61000-4-2, Contact Discharge (Connector Pins)
    • ±15 kV - IEC 61000-4-2, Air-Gap Discharge (Connector Pins)
    • ±15 kV - Human-Body Model (Connector Pins)
  • Auto-Power-Up Feature Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at A9–A13 Pins
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection
    • ±4 kV - Human-Body Model
    • ±8 kV - IEC 61000-4-2, Contact Discharge (Connector Pins)
    • ±15 kV - IEC 61000-4-2, Air-Gap Discharge (Connector Pins)
    • ±15 kV - Human-Body Model (Connector Pins)

The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer-system errors caused by deasserting the BUSY signal in the cable at power on.

The SN74LVCE161284 is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer-system errors caused by deasserting the BUSY signal in the cable at power on.
filter 查找其他 应用特定的电压转换器
下载 观看带字幕的视频 视频

技术文档

star =有关此米6体育平台手机版_好二三四的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 34
类型 标题 下载最新的英语版本 日期
* 数据表 SN74LVCE161284 数据表 2004年 1月 19日
应用手册 原理图检查清单 - 使用固定或方向控制转换器进行设计的指南 PDF | HTML 英语版 PDF | HTML 2024年 10月 3日
应用手册 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
应用手册 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
应用手册 了解 CMOS 输出缓冲器中的瞬态驱动强度与直流驱动强度 PDF | HTML 最新英语版本 (Rev.A) PDF | HTML 2024年 5月 15日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
选择指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
选择指南 Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 How to Select Little Logic (Rev. A) 2016年 7月 26日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
选择指南 小尺寸逻辑器件指南 (Rev. E) 最新英语版本 (Rev.G) 2012年 7月 16日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 CMOS 非缓冲反向器在振荡器电路中的使用 英语版 2006年 3月 23日
应用手册 选择正确的电平转换解决方案 (Rev. A) 英语版 (Rev.A) 2006年 3月 23日
米6体育平台手机版_好二三四概述 Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
用户指南 LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002年 12月 18日
应用手册 Texas Instruments Little Logic Application Report 2002年 11月 1日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
更多文献资料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
应用手册 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
应用手册 Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
更多文献资料 STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
应用手册 Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
应用手册 LVC Characterization Information 1996年 12月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
设计指南 Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
应用手册 Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

仿真模型

HSPICE MODEL OF SN74LVCE161284

SCEJ197.ZIP (234 KB) - HSpice Model
下载
封装 引脚 CAD 符号、封装和 3D 模型
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频