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TMS320C6412

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C64x 定点 DSP- 高达 720MHz、McBSP、McASP、I2cC、以太网

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TMS320C6412

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米6体育平台手机版_好二三四详情

DSP type 1 C64x DSP (max) (MHz) 500, 600, 720 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 PCIe 1 PCI Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x DSP (max) (MHz) 500, 600, 720 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 PCIe 1 PCI Rating Catalog Operating temperature range (°C) -40 to 105
OMFCBGA (GDK) 548 529 mm² 23 x 23 OMFCBGA (GNZ) 548 729 mm² 27 x 27 OMFCBGA (ZDK) 548 529 mm² 23 x 23 OMFCBGA (ZNZ) 548 729 mm² 27 x 27
  • High-Performance Digital Media Processor (TMS320C6412)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-500)
  • 3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
  • High-Performance Digital Media Processor (TMS320C6412)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Inter-Integrated Circuit (I2C) Bus
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal (-500)
  • 3.3-V I/Os, 1.4-V Internal (A-500, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320C64x™DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI™ architecture. The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The ethernet media access controller (EMAC) provides an efficient interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320C6412 Fixed-Point Digital Signal Processor 数据表 (Rev. J) 2010年 10月 12日
* 勘误表 TMS320C6412 DSP Silicon Errata (Silicon Revisions 2.0, 1.2, 1.1, 1.0) (Rev. J) 2010年 2月 4日
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 英语版 (Rev.A) PDF | HTML 2021年 5月 19日
用户指南 Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012年 8月 9日
应用手册 Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010年 7月 30日
用户指南 TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009年 7月 2日
应用手册 TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 2007年 9月 4日
应用手册 Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007年 5月 20日
用户指南 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007年 4月 11日
米6体育平台手机版_好二三四概述 TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007年 4月 4日
用户指南 TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 2007年 3月 26日
用户指南 TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C) 2007年 1月 25日
用户指南 TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 2006年 12月 14日
用户指南 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006年 11月 15日
用户指南 TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) 2006年 2月 28日
用户指南 TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006年 1月 1日
用户指南 TMS320C6000 DSP 外设概述参考指南 (Rev. H) 最新英语版本 (Rev.Q) 2005年 11月 7日
应用手册 TMS320C6412 Hardware Designer's Resource Guide (Rev. A) 2005年 10月 21日
应用手册 Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005年 10月 20日
用户指南 TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005年 3月 1日
应用手册 TMS320C6412 Power Consumption Summary (Rev. E) 2005年 1月 27日
用户指南 TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005年 1月 25日
应用手册 Use and Handling of Semiconductor Packages With ENIG Pad Finishes 2004年 8月 31日
用户指南 TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 2004年 8月 13日
应用手册 TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 2004年 4月 26日
应用手册 TMS320C6000 Board Design: Considerations for Debug (Rev. C) 2004年 4月 21日
用户指南 TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) 2004年 3月 26日
用户指南 TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 2004年 3月 25日
应用手册 TMS320C6000 McBSP Initialization (Rev. C) 2004年 3月 8日
应用手册 TMS320C6000 EDMA IO Scheduling and Performance 2004年 3月 5日
应用手册 TMS320C64x EDMA Performance Data 2004年 3月 5日
应用手册 TMS320C64x EDMA Architecture 2004年 3月 3日
应用手册 TMS320C64x DSP Peripheral Component Interconnect (PCI) Performance 2003年 10月 31日
应用手册 TMS320C64x DSP Host Port Interface (HPI) Performance 2003年 10月 24日
用户指南 TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 2003年 7月 31日
用户指南 TMS320C6000 DSP Cache User's Guide (Rev. A) 2003年 5月 5日
应用手册 Using IBIS Models for Timing Analysis (Rev. A) 2003年 4月 15日
应用手册 TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 2002年 6月 4日
应用手册 TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 2002年 4月 17日
应用手册 TMS320C6000 Board Design for JTAG (Rev. C) 2002年 4月 2日
应用手册 TMS320C6000 EMIF to External Flash Memory (Rev. A) 2002年 2月 13日
应用手册 Cache Usage in High-Performance DSP Applications with the TMS320C64x 2001年 12月 13日
应用手册 Using a TMS320C6000 McBSP for Data Packing (Rev. A) 2001年 10月 31日
应用手册 TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 2001年 10月 24日
应用手册 Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 2001年 9月 30日
应用手册 TMS320C6000 Host Port to MC68360 Interface (Rev. A) 2001年 9月 30日
应用手册 TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 2001年 8月 31日
应用手册 TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 2001年 8月 31日
应用手册 Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 2001年 8月 31日
应用手册 TMS320C6000 System Clock Circuit Example (Rev. A) 2001年 8月 15日
应用手册 TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 2001年 7月 23日
应用手册 TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 2001年 7月 10日
应用手册 TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 2001年 6月 30日
应用手册 TMS320C6000 Host Port to MPC860 Interface (Rev. A) 2001年 6月 21日
应用手册 TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 2001年 5月 21日
用户指南 TMS320C64x Technical Overview (Rev. B) 2001年 1月 30日
应用手册 Circular Buffering on TMS320C6000 (Rev. A) 2000年 9月 12日
应用手册 TMS320C6000 McBSP as a TDM Highway (Rev. A) 2000年 9月 11日
应用手册 TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 2000年 2月 2日
应用手册 General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 2000年 1月 31日
应用手册 TMS320C6000 C Compiler: C Implementation of Intrinsics 1999年 12月 7日
应用手册 TMS320C6000 McBSP: I2S Interface 1999年 9月 8日

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所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪，需要 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (480Mbps) (...)

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XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

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SPRC090 — Download TMS320C6000 Chip Support Library

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支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
数字信号处理器 (DSP)
TMS320C6412 — C64x 定点 DSP- 高达 720MHz、McBSP、McASP、I2cC、以太网 TMS320C6414 — C64x 定点 DSP - 高达 720MHz、McBSP TMS320C6414T — C64x 定点 DSP - 高达 1GHz、McBSP TMS320C6415 — C64x 定点 DSP - 高达 720MHz、McBSP、PCI TMS320C6415T — C64x 定点 DSP - 高达 850MHz、McBSP、PCI TMS320C6416 — C64x 定点 DSP - 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6416T — C64x 定点 DSP - 高达 850MHz、McBSP、PCI、VCP/TCP TMS320C6701 — C67x 浮点 DSP - 高达 167MHz、McBSP TMS320DM640 — 视频/成像定点数字信号处理器 TMS320DM641 — 视频/成像定点数字信号处理器 TMS320DM642 — 视频/成像定点数字信号处理器 TMS320DM642Q — 视频/成像定点数字信号处理器
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SPRC122 — C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

米6体育平台手机版_好二三四
数字信号处理器 (DSP)
SM320C6201-EP — 增强型米6体育平台手机版_好二三四 C6201 定点 DSP SM320C6455-EP — 增强型米6体育平台手机版_好二三四 C6455 定点 DSP SMJ320C6201B — 军用定点数字信号处理器 SMJ320C6203 — 军用级 C62x 定点 DSP - 陶瓷封装 TMS320C6202B — C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B — C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 — 定点数字信号处理器 TMS320C6205 — 定点数字信号处理器 TMS320C6211B — C62x 定点 DSP- 高达 167MHz TMS320C6412 — C64x 定点 DSP- 高达 720MHz、McBSP、McASP、I2cC、以太网 TMS320C6414 — C64x 定点 DSP - 高达 720MHz、McBSP TMS320C6414T — C64x 定点 DSP - 高达 1GHz、McBSP TMS320C6415 — C64x 定点 DSP - 高达 720MHz、McBSP、PCI TMS320C6415T — C64x 定点 DSP - 高达 850MHz、McBSP、PCI TMS320C6416 — C64x 定点 DSP - 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6416T — C64x 定点 DSP - 高达 850MHz、McBSP、PCI、VCP/TCP TMS320C6421 — C64x+ 定点 DSP - 高达 600MHz、8 位 EMIFA、16 位 DDR2、SDRAM TMS320C6421Q — C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424 — C64x+ 定点 DSP - 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2、SDRAM TMS320C6424Q — C64x+ 定点 DSP - 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6452 — C64x+ 定点 DSP- 高达 900MHz、1Gbps 以太网 TMS320C6454 — C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6455 — C64x+ 频率高达 1.2GHz、具有 64 位 EMIFA、32 位和 16 位 DDR2、1Gbps 以太网的定点 DSP TMS320C6457 — 通信基础设施数字信号处理器 TMS320C6474 — 多核数字信号处理器 TMS320DM640 — 视频/成像定点数字信号处理器 TMS320DM641 — 视频/成像定点数字信号处理器 TMS320DM642 — 视频/成像定点数字信号处理器 TMS320DM642Q — 视频/成像定点数字信号处理器 TMS320DM6431 — 数字媒体处理器 TMS320DM6431Q — 数字媒体处理器，性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6433 — 数字媒体处理器 TMS320DM6435 — 数字媒体处理器 TMS320DM6435Q — 数字媒体处理器，性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437 — 数字媒体处理器 TMS320DM6437Q — 数字媒体处理器，性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 — 达芬奇数字媒体片上系统 TMS320DM6443 — 达芬奇数字媒体片上系统 TMS320DM6446 — 达芬奇数字媒体片上系统
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SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
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驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
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驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

支持的米6体育平台手机版_好二三四和硬件

支持的米6体育平台手机版_好二三四和硬件

此设计资源支持这些类别中的大部分米6体育平台手机版_好二三四。

查看米6体育平台手机版_好二三四详情页，验证是否能提供支持。
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软件编解码器

ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器

Adaptive Digital 是音质增强算法的开发公司，提供可与 TI DSP 配合使用的一流声学回声消除软件。Adaptive Digital 在算法开发、实施、优化和配置调优方面具有丰富的经验。他们提供适用于语音技术、音质软件、回声消除、会议软件、语音压缩算法的解决方案和即用型解决方案。

如需了解有关 Adaptive Digital 的更多信息，请访问 https://www.adaptivedigital.com。

来源：Adaptive Digital Technologies, Inc.
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软件编解码器

VOCAL-3P-DSPVOIPCODECS — Vocal Technologies DSP VoIP 编解码器

经过 25 年以上的组装和 C 代码开发，VOCAL 的模块化软件套件可用于各种各样的 TI DSP 米6体育平台手机版_好二三四。米6体育平台手机版_好二三四具体包括 ATA、VoIP 服务器和网关、基于 HPNA 的 IPBX、视频监控、语音和视频会议、语音和数据射频器件、RoIP 网关、政务安全器件、合法拦截软件、医疗设备、嵌入式调制解调器、T.38 传真和 FoIP。

如需了解有关 Vocal Technologies 的更多信息，请访问 https://www.vocal.com。

来源：VOCAL Technologies, Ltd.
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仿真模型

C6412 GDK BSDL Model

SPRM123.ZIP (9 KB) - BSDL Model
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仿真模型

C6412 GDK/GNZ IBIS Model

SPRM110.ZIP (109 KB) - IBIS Model
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仿真模型

C6412 GNZ BSDL Model

SPRM122.ZIP (9 KB) - BSDL Model
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封装 引脚 CAD 符号、封装和 3D 模型
OMFCBGA (GDK) 548 Ultra Librarian
OMFCBGA (GNZ) 548 Ultra Librarian
OMFCBGA (ZDK) 548 Ultra Librarian
OMFCBGA (ZNZ) 548 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频