SNAS519H July   2011  – August 2015 ADC12D1000RF , ADC12D1600RF

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Static Converter
    6. 4.6  Electrical Characteristics: Dynamic Converter
    7. 4.7  Electrical Characteristics: Analog Input/Output and Reference
    8. 4.8  Electrical Characteristics: I-Channel to Q-Channel
    9. 4.9  Electrical Characteristics: Sampling Clock
    10. 4.10 Electrical Characteristics: AutoSync Feature
    11. 4.11 Electrical Characteristics: Digital Control and Output Pin
    12. 4.12 Electrical Characteristics: Power Supply
    13. 4.13 Electrical Characteristics: AC
    14. 4.14 Timing Requirements: Serial Port Interface
    15. 4.15 Timing Requirements: Calibration
    16. 4.16 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Input Control and Adjust
        1. 5.3.1.1 AC- and DC-coupled Mode
        2. 5.3.1.2 Input Full-Scale Range Adjust
        3. 5.3.1.3 Input Offset Adjust
        4. 5.3.1.4 DES Timing Adjust
        5. 5.3.1.5 Sampling Clock Phase Adjust
      2. 5.3.2 Output Control and Adjust
        1. 5.3.2.1 SDR / DDR Clock
        2. 5.3.2.2 LVDS Output Differential Voltage
        3. 5.3.2.3 LVDS Output Common-Mode Voltage
        4. 5.3.2.4 Output Formatting
        5. 5.3.2.5 Test Pattern Mode
        6. 5.3.2.6 Time Stamp
      3. 5.3.3 Calibration Feature
        1. 5.3.3.1 Calibration Control Pins and Bits
        2. 5.3.3.2 How to Execute a Calibration
        3. 5.3.3.3 Power-on Calibration
        4. 5.3.3.4 On-Command Calibration
        5. 5.3.3.5 Calibration Adjust
        6. 5.3.3.6 Read/Write Calibration Settings
        7. 5.3.3.7 Calibration and Power Down
        8. 5.3.3.8 Calibration and the Digital Outputs
      4. 5.3.4 Power Down
    4. 5.4 Device Functional Modes
      1. 5.4.1 DES and Non-DES Mode
      2. 5.4.2 Demux and Non-Demux Mode
    5. 5.5 Programming
      1. 5.5.1 Control Modes
        1. 5.5.1.1 Non-Extended Control Mode
          1. 5.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 5.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 5.5.1.1.3  Dual Data Rate Phase Pin (DDRPh)
          4. 5.5.1.1.4  Calibration Pin (CAL)
          5. 5.5.1.1.5  Calibration Delay Pin (CalDly)
          6. 5.5.1.1.6  Power-Down I-channel Pin (PDI)
          7. 5.5.1.1.7  Power-Down Q-channel Pin (PDQ)
          8. 5.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 5.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 5.5.1.1.10 AC- and DC-Coupled Mode Pin (VCMO)
          11. 5.5.1.1.11 LVDS Output Common-mode Pin (VBG)
        2. 5.5.1.2 Extended Control Mode
          1. 5.5.1.2.1 The Serial Interface
    6. 5.6 Register Maps
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 The Analog Inputs
        1. 6.1.1.1 Acquiring the Input
        2. 6.1.1.2 Driving the ADC in DES Mode
        3. 6.1.1.3 FSR and the Reference Voltage
        4. 6.1.1.4 Out-Of-Range Indication
        5. 6.1.1.5 Maximum Input Range
        6. 6.1.1.6 AC-Coupled Input Signals
        7. 6.1.1.7 DC-Coupled Input Signals
        8. 6.1.1.8 Single-Ended Input Signals
      2. 6.1.2 The Clock Inputs
        1. 6.1.2.1 CLK Coupling
        2. 6.1.2.2 CLK Frequency
        3. 6.1.2.3 CLK Level
        4. 6.1.2.4 CLK Duty Cycle
        5. 6.1.2.5 CLK Jitter
        6. 6.1.2.6 CLK Layout
      3. 6.1.3 The LVDS Outputs
        1. 6.1.3.1 Common-Mode and Differential Voltage
        2. 6.1.3.2 Output Data Rate
        3. 6.1.3.3 Terminating Unused LVDS Output Pins
      4. 6.1.4 Synchronizing Multiple ADC12D1x00RFS in a System
        1. 6.1.4.1 AutoSync Feature
        2. 6.1.4.2 DCLK Reset Feature
      5. 6.1.5 Recommended System Chips
        1. 6.1.5.1 Temperature Sensor
        2. 6.1.5.2 Clocking Device
        3. 6.1.5.3 Amplifiers for the Analog Input
        4. 6.1.5.4 Balun Recommendations for Analog Input
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
    1. 7.1 System Power-on Considerations
      1. 7.1.1 Power-on, Configuration, and Calibration
      2. 7.1.2 Power-on and Data Clock (DCLK)
    2. 7.2 Supply Voltage
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 Power Planes
      2. 8.1.2 Bypass Capacitors
      3. 8.1.3 Ground Planes
      4. 8.1.4 Power System Example
    2. 8.2 Layout Example
    3. 8.3 Thermal Management
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Specification Definitions
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Related Links
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz
  • Configurable to Either 3.2 or 2 GSPS Interleaved or 1600 or 1000 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible With ADC10D1x00, ADC12D1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 3.2- and 2-GSPS ADC
      • IMD3 (Fin = 2.7 GHz at –13 dBFS) –63.7/–73 dBFS (Typical)
      • IMD3 (Fin = 2.7 GHz at –16 dBFS) –66.7/–85 dBFS (Typical)
      • Noise Floor –154.6/–154 dBm/Hz (Typical)
      • Power 3.94/3.42 W (Typical)
    • Dual 1600/1000 MSPS ADC, Fin = 498 MHz
      • ENOB 9.2/9.4 Bits (Typical)
      • SNR 58.2/58.8 dB (Typical)
      • SFDR 66.7/71.9 dBc (Typical)
      • Power per Channel 1.97/1.71 W (Typical)

1.2 Applications

  • 3G/4G Wireless Basestations
    • Receive Path
    • DPD Path
  • Wideband Microwave Backhaul
  • RF Sampling Software Defined Radios
  • Military Communications
  • SIGINT
  • RADAR and LIDAR
  • Wideband Communications
  • Consumer RFs
  • Tests and Measurements

1.3 Description

The 12-bit 3.2- and 2-GSPS ADC12D1x00RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D1x00RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 3rd Nyquist zone

The ADC12D1x00RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common-mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
ADC12D1000RF BGA (40) 27.00 mm × 27.00 mm
ADC12D1600RF
(1) For more information, see Section 10, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

ADC12D1000RF ADC12D1600RF 30164411.png
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