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DLPC6401 DLP® Data Processor
DLPS031C
December 2013 – August 2015
DLPC6401
PRODUCTION DATA.
CONTENTS
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DLPC6401 DLP® Data Processor
1
Features
2
Applications
3
Description
Device Images
Typical Application Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Electrical Characteristics (Normal Mode)
6.7
System Oscillators Timing Requirements
6.8
Test and Reset Timing Requirements
6.9
JTAG Interface: I/O Boundary Scan Application Timing Requirements
6.10
Port 1 Input Pixel Interface Timing Requirements
6.11
Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
6.12
Synchronous Serial Port (SSP) Interface Timing Requirements
6.13
Programmable Output Clocks Switching Characteristics
6.14
Synchronous Serial Port (SSP) Interface Switching Characteristics
6.15
JTAG Interface: I/O Boundary Scan Application Switching Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
System Reset Operation
7.3.1.1
Power-Up Reset Operation
7.3.1.2
System Reset Operation
7.3.1.3
Spread Spectrum Clock Generator Support
7.3.1.4
GPIO Interface
7.3.1.5
Source Input Blanking
7.3.1.6
Video and Graphics Processing Delay
7.3.2
Program Memory Flash/SRAM Interface
7.3.2.1
Calibration and Debug Support
7.3.2.2
Board-Level Test Support
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Recommended MOSC Crystal Oscillator Configuration
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
9
Power Supply Recommendations
9.1
System Power Regulation
9.2
System Power-Up Sequence
9.3
Power-On Sense (POSENSE) Support
9.4
System Environment and Defaults
9.4.1
DLPC6401 System Power-Up and Reset Default Conditions
9.4.2
1.2-V System Power
9.4.3
1.8-V System Power
9.4.4
1.9-V System Power
9.4.5
3.3-V System Power
9.4.6
FPD-Link Input LVDS System Power
9.4.7
Power Good (PWRGOOD) Support
9.4.8
5-V Tolerant Support
10
Layout
10.1
Layout Guidelines
10.1.1
PCB Layout Guidelines for Internal ASIC Power
10.1.2
PCB Layout Guidelines for Quality Auto-Lock Performance
10.1.3
DMD Interface Considerations
10.1.4
General Handling Guidelines for Unused CMOS-Type Pins
10.2
Layout Example
10.3
Thermal Considerations
11
Device and Documentation Support
11.1
Device Support
11.1.1
Device Nomenclature
11.1.1.1
Video Timing Parameter Definitions
11.1.1.2
Device Marking
11.2
Community Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
12.1.1
Packaging Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
ZFF|419
MPBGAF9
Thermal pad, mechanical data (Package|Pins)
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