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DS90UB914A-Q1 25-MHz to 100-MHz 10- and 12-Bit FPD-Link III Deserializer
SNLS499D
April 2016 – October 2019
DS90UB914A-Q1
PRODUCTION DATA.
CONTENTS
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DS90UB914A-Q1 25-MHz to 100-MHz 10- and 12-Bit FPD-Link III Deserializer
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions: DS90UB914A-Q1 Deserializer
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
AC Timing Specifications (SCL, SDA) - I2C-Compatible
7.7
Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible
7.8
Deserializer Switching Characteristics
7.9
Typical Characteristics
8
Parameter Measurement Information
8.1
Timing Diagrams and Test Circuits
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Serial Frame Format
9.3.2
Line Rate Calculations for the DS90UB913A/914A
9.3.3
Deserializer Multiplexer Input
9.3.4
Error Detection
9.3.5
Synchronizing Multiple Cameras
9.3.6
General-Purpose I/O (GPIO) Descriptions
9.3.7
LVCMOS VDDIO Option
9.3.8
EMI Reduction
9.3.8.1
Deserializer Staggered Output
9.3.8.2
Spread Spectrum Clock Generation (SSCG) on the Deserializer
9.3.9
Pixel Clock Edge Select (TRFB / RRFB)
9.3.10
Power Down
9.4
Device Functional Modes
9.4.1
DS90UB913A/914A Operation With External Oscillator as Reference Clock
9.4.2
DS90UB913A/914A Operation With Pixel Clock From Imager as Reference Clock
9.4.3
MODE Pin on Deserializer
9.4.4
Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select (OSS_SEL)
9.4.5
Built-In Self Test
9.4.6
BIST Configuration and Status
9.4.7
Sample BIST Sequence
9.5
Programming
9.5.1
Programmable Controller
9.5.2
Description of Bidirectional Control Bus and I2C Modes
9.5.3
I2C Pass-Through
9.5.4
Slave Clock Stretching
9.5.5
ID[x] Address Decoder on the Deserializer
9.5.6
Multiple Device Addressing
9.6
Register Maps
10
Application and Implementation
10.1
Application Information
10.1.1
Power Over Coax
10.1.2
Power-Up Requirements and PDB Pin
10.1.3
AC Coupling
10.1.4
Transmission Media
10.1.5
Adaptive Equalizer – Loss Compensation
10.2
Typical Applications
10.2.1
Coax Application
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.3
Application Curves
10.2.2
STP Application
10.2.2.1
Design Requirements
10.2.2.2
Detailed Design Procedure
10.2.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.1.1
Interconnect Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Documentation Support
13.1.1
Related Documentation
13.2
Receiving Notification of Documentation Updates
13.3
Community Resources
13.4
Trademarks
13.5
Electrostatic Discharge Caution
13.6
Glossary
14
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RHS|48
MPQF159B
Thermal pad, mechanical data (Package|Pins)
RHS|48
QFND509A
Orderable Information
snls499d_oa
snls499d_pm
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