SLLS949C
September 2009 – January 2023
TPD2S017
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Dissipation Ratings
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Support Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DBV|6
MPDS026Q
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slls949c_oa
slls949c_pm
1
Features
Ultra-low clamping voltage ensures the protection of ultra-low voltage core chipset during ESD events
IEC 61000-4-2 ESD protection
Matching of series resistor (R = 1 Ω) of ±8 mΩ (typical)
Differential channel input capacitance matching of 0.02 pF (typical)
High-speed data rate and EMI filter action at high frequencies (–3 dB bandwidth, ≉3 GHz)
Available in 6-Pin small-outline transistor [SOT-23 (DBV)] package
Easy straight-through routing packages
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