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TPD4E002 Quad Low-Capacitance Array with ±15-kV ESD Protection
SLVS615F
July 2006 – December 2016
TPD4E002
PRODUCTION DATA.
CONTENTS
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TPD4E002 Quad Low-Capacitance Array with ±15-kV ESD Protection
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings—JEDEC Specification
6.3
ESD Ratings—IEC Specification
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Electrical Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Signal Range on I/O1 Through I/O2
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
DRL|5
MPDS158G
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvs615f_oa
slvs615f_pm
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