SBASAE7
August 2022
ADS131M02-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Switching Characteristics
6.8
Timing Diagrams
6.9
Typical Characteristics
7
Parameter Measurement Information
7.1
Noise Measurements
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Input ESD Protection Circuitry
8.3.2
Input Multiplexer
8.3.3
Programmable Gain Amplifier (PGA)
8.3.4
Voltage Reference
8.3.5
Clocking and Power Modes
8.3.6
ΔΣ Modulator
8.3.7
Digital Filter
8.3.7.1
Digital Filter Implementation
8.3.7.1.1
Fast-Settling Filter
8.3.7.1.2
SINC3 and SINC3 + SINC1 Filter
8.3.7.2
Digital Filter Characteristic
8.3.8
DC Block Filter
8.3.9
Internal Test Signals
8.3.10
Channel Phase Calibration
8.3.11
Calibration Registers
8.3.12
Communication Cyclic Redundancy Check (CRC)
8.3.13
Register Map CRC
8.4
Device Functional Modes
8.4.1
Power-Up and Reset
8.4.1.1
Power-On Reset
8.4.1.2
SYNC/RESET Pin
8.4.1.3
RESET Command
8.4.2
Fast Start-Up Behavior
8.4.3
Conversion Modes
8.4.3.1
Continuous-Conversion Mode
8.4.3.2
Global-Chop Mode
8.4.4
Power Modes
8.4.5
Standby Mode
8.4.6
Current-Detect Mode
8.5
Programming
8.5.1
Interface
8.5.1.1
Chip Select (CS)
8.5.1.2
Serial Data Clock (SCLK)
8.5.1.3
Serial Data Input (DIN)
8.5.1.4
Serial Data Output (DOUT)
8.5.1.5
Data Ready (DRDY)
8.5.1.6
Conversion Synchronization or System Reset (SYNC/RESET)
8.5.1.7
SPI Communication Frames
8.5.1.8
SPI Communication Words
8.5.1.9
ADC Conversion Data
8.5.1.9.1
Collecting Data for the First Time or After a Pause in Data Collection
8.5.1.10
Commands
8.5.1.10.1
NULL (0000 0000 0000 0000)
8.5.1.10.2
RESET (0000 0000 0001 0001)
8.5.1.10.3
STANDBY (0000 0000 0010 0010)
8.5.1.10.4
WAKEUP (0000 0000 0011 0011)
8.5.1.10.5
LOCK (0000 0101 0101 0101)
8.5.1.10.6
UNLOCK (0000 0110 0101 0101)
8.5.1.10.7
RREG (101a aaaa annn nnnn)
8.5.1.10.7.1
Reading a Single Register
8.5.1.10.7.2
Reading Multiple Registers
8.5.1.10.8
WREG (011a aaaa annn nnnn)
8.5.1.11
Short SPI Frames
8.5.2
Synchronization
8.6
ADS131M02-Q1 Registers
9
Application and Implementation
9.1
Application Information
9.1.1
Unused Inputs and Outputs
9.1.2
Antialiasing
9.1.3
Minimum Interface Connections
9.1.4
Multiple Device Configuration
9.1.5
Troubleshooting
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Current Shunt Measurement
9.2.2.2
Battery Pack Voltage Measurement
9.2.3
Application Curve
9.3
Power Supply Recommendations
9.3.1
CAP Pin Behavior
9.3.2
Power-Supply Sequencing
9.3.3
Power-Supply Decoupling
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|20
MPDS362A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sbasae7_oa
sbasae7_pm
1
Features
AEC-Q100 qualified for automotive applications:
Temperature grade 1: –40°C to +125°C, T
A
Functional Safety-Capable
Documentation available to aid functional safety system design
2
simultaneously sampling differential inputs
Programmable data rate up to 64 kSPS
Programmable gain up to 128
Noise performance:
102-dB dynamic range at gain = 1, 4 kSPS
80-dB dynamic range at gain = 64, 4 kSPS
Total harmonic distortion: –100 dB
High-impedance inputs for direct sensor connection:
330-kΩ input impedance for gains of
1, 2, and 4
≥1-MΩ input impedance for gains of
8, 16, 32, 64, and 128
Programmable channel-to-channel phase delay calibration:
Resolution = 244 ns, f
CLKIN
= 8.192 MHz
Fast start-up: First data within 0.5 ms of supply ramp
Integrated negative charge pump allows input signals below ground
Crosstalk between channels: –120 dB
Low-drift internal voltage reference
Cyclic redundancy check (CRC) on communications and register map
Analog and digital supplies: 2.7 V to 3.6 V
Low-power consumption: 2.3 mW at 3-V AVDD and DVDD
Package: 20-pin TSSOP
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