1 Features

Set-reset capability
Static flip-flop operation – retains state indefinitely with clock level either high or low
Medium speed operation – 16 MHz (typical) clock toggle rate at 10 V
Standardized symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package-temperature range):
- 1 V at V_DD = 5 V
- 2 V at V_DD = 10 V
- 2.5 V at V_DD = 15 V
5 V, 10 V, and 15 V parametric ratings
Meets all requirements of JEDEC tentative standard No. 138, standard specifications for description of 'B' series CMOS devices