SCHS138D November   1998  – March 2022 CD74HC93 , CD74HCT93

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • N|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Can be configured to divide by 2, 8, and 16
  • Asynchronous reset
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: – 55°C to 125°C
  • Balances propagation delay and transition times
  • Signigicant power reduction compared to LSTTL logic ICs
  • HC types
    • 2 V to 6 V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC
  • HCT types
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH
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