SCHS167G November   1998  – October 2022 CD54HC240 , CD54HC244 , CD54HCT240 , CD54HCT241 , CD54HCT244 , CD74HC240 , CD74HC241 , CD74HC244 , CD74HCT240 , CD74HCT241 , CD74HCT244

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics '240
    5. 5.5 Electrical Characteristics '241
    6. 5.6 Electrical Characteristics '244
    7. 5.7 Switching Characteristics '240
    8. 5.8 Switching Characteristics '241
    9. 5.9 Switching Characteristics '244
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|20
  • DW|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • HC/HCT240 Inverting
  • HC/HCT241 Non-inverting
  • HC/HCT244 Non-inverting
  • Typical propagation delay = 8ns at VCC = 5 V,
    CL = 15 pF, TA = 25℃ for HC240
  • Three-state outputs
  • Buffered inputs
  • High-current bus driver outputs
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types:
    • 2 V to 6 V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types:
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility,
      VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1μA at VOL, VOH
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