SCAS877F May 2009 – January 2016 CDCLVP1216
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: LVCMOS Input
- 6.6 Electrical Characteristics: Differential Input
- 6.7 Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V
- 6.8 Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V
- 6.9 Timing Requirements, at VCC = 2.375 V to 2.625 V
- 6.10 Timing Requirements, at VCC = 3 V to 3.6 V
- 6.11 Pin Characteristics
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Applications and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
- 14Mechanical, Packaging, and Orderable Information
1 Features
- 2:16 Differential Buffer
- Selectable Clock Inputs Through Control Pin
- Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
- 16 LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 110 mA
- Very Low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz Offset Range:
- 57 fs, RMS (Typical) at 122.88 MHz
- 48 fs, RMS (Typical) at 156.25 MHz
- 30 fs, RMS (Typical) at 312.5 MHz
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 550 ps
- Maximum Output Skew: 30 ps
- LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
- Industrial Temperature Range: –40°C to +85°C
- Supports 105°C PCB Temperature (Measured with a Thermal Pad)
- ESD Protection Exceeds 2000 V (HBM)
- Available in 7-mm × 7-mm VQFN-48 (RGZ) Package
2 Applications
- Wireless Communications
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
3 Description
The CDCLVP1216 is a highly versatile, low additive jitter buffer that can generate 16 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1216 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 30 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVPECL clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVP1216 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1216 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1216 is packaged in a small 48-pin,
7-mm x 7-mm VQFN package and is characterized for operation from –40°C to +85°C.
Device Information(1)
| ORDER NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| CDCLVP1216 | VQFN (48) | 7.00 mm x 7.00 mm |
Functional Block Diagram
Differential Output Peak-to-Peak Voltage
vs Frequency
