DAC121S101/-Q1 12-Bit Micro Power, RRO Digital-to-Analog Converter
- SNAS265J June 2005 – September 2015 DAC121S101 , DAC121S101-Q1
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

DAC121S101/-Q1 12-Bit Micro Power, RRO Digital-to-Analog Converter

1 Features

DAC121S101-Q1 is AEC-Q100 Grade 1 Qualified and is Manufactured on an Automotive Grade Flow.
Ensured Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-on Reset to Zero Volts Output
Wide Temperature Range of −40°C to +125°C
Wide Power Supply Range of 2.7 V to 5.5 V
Small Packages
Power Down Feature
Key Specifications
- 12-Bit Resolution
- DNL -0.15, +0.25 LSB (Typical)
- 8-µs Output Settling Time (Typical)
- 4-mV Zero Code Error (Typical)
- Full-Scale Error at −0.06 %FS (Typical)
- 0.64-mW (3.6-V) / 1.43-mW (5.5-V) Normal Mode Power Consumption (Typical)
- 0.14-µW (3.6-V) / 0.39-µW (5.5-V) Power-Down Mode (Typical)

2 Applications

Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Automotive

3 Description

The DAC121S101 device is a full-featured, general-purpose, 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes just 177 µA of current at 3.6 V. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPI™, QSPI, MICROWIRE and DSP interfaces. Competitive devices are limited to 20-MHz clock rates at supply voltages in the 2.7 V to 3.6 V range.

The supply voltage for the DAC121S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt.

The low power consumption and small packages of the DAC121S101 make it an excellent choice for use in battery operated equipment.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DAC121S101	SOT (6)	2.90 mm × 1.60 mm
DAC121S101	VSSOP (8)	3.00 mm × 3.00 mm
DAC121S101-Q1	SOT (6)	2.90 mm × 1.60 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Block Diagram

DNL vs. Output Code

4 Revision History

Changes from I Revision (March 2013) to J Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from H Revision (February 2010) to I Revision

Changed layout of National Data Sheet to TI formatGo

5 Description continued

The DAC121S101 is a direct replacement for the AD5320 and the DAC7512 and is one of a family of pin compatible DACs, including the 8-bit DAC081S101 and the 10-bit DAC101S101. The DAC121S101 operates over the extended industrial temperature range of −40°C to +105°C while the DAC121S101-Q1 operates over the Grade 1 automotive temperature range of −40°C to +125°C. The DAC121S101 is available in a 6-lead SOT and an 8-lead VSSOP and the DAC121S101-Q1 is available in the 6-lead SOT only.

6 Pin Configuration and Functions

DDC Package

6-Pin SOT

Top View

DAC121S101 (Only) DGK Package

8-Pin VSSOP

Top View

Pin Functions

PIN			I/O	DESCRIPTION
NAME	SOT NO.	VSSOP NO.	I/O	DESCRIPTION
D_IN	4	7	Input	Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
GND	2	8	—	Ground reference for all on-chip circuitry.
NC	—	2	—	No Connect. There is no internal connection to these pins.
NC	—	3	—	No Connect. There is no internal connection to these pins.
SCLK	5	6	Input	Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.
SYNC	6	5	Input	Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
V_A	3	1	—	Power supply and Reference input. Should be decoupled to GND.
V_OUT	1	4	Output	DAC Analog Output Voltage.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
Supply Voltage, V_A		6.5	V
Voltage on any Input Pin	−0.3	(V_A + 0.3)	V
Input Current at Any Pin ⁽³⁾		10	mA
Package Input Current ⁽³⁾		20	mA
Power Consumption at T_A = 25°C	See ⁽⁴⁾
Soldering Temperature, Infrared, 10 Seconds⁽⁵⁾		235	°C
Storage Temperature, T_stg	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Machine Model	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾ ⁽²⁾

		MIN	NOM	MAX	UNIT
Operating Temperature Range	DAC121S101	−40	T_A	105	°C
Operating Temperature Range	DAC121S101-Q1	−40	T_A	125	°C
Supply Voltage, V_A		2.7		5.5	V
Any Input Voltage⁽⁶⁾		−0.1		(V_A + 0.1)	V
Output Load		0		1500	pF
SCLK Frequency				30	MHz

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		DAC121S101, DAC121S101-Q1		UNIT
		DGK (VSSOP)	DDC (SOT)
		8 PINS	6 PINS
R_θJA	Junction-to-ambient thermal resistance	240	250	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

The following specifications apply for V_A = 2.7 V to 5.5 V, R_L = 2 kΩ to GND, C_L = 200 pF to GND, f_SCLK = 30 MHz, input code range 48 to 4047. All limits are for T_A = 25°C, unless otherwise specified.

PARAMETER		TEST CONDITIONS			MIN⁽⁷⁾	TYP⁽⁷⁾	MAX⁽⁷⁾	UNIT
STATIC PERFORMANCE
	Resolution	T_MIN ≤ T_A ≤ T_MAX			12			Bits
	Monotonicity	T_MIN ≤ T_A ≤ T_MAX			12			Bits
INL	Integral Non-Linearity	Over Decimal codes 48 to 4047		T_A = 25°C			±2.6	LSB
INL	Integral Non-Linearity	Over Decimal codes 48 to 4047		T_MIN ≤ T_A ≤ T_MAX			±8	LSB
DNL	Differential Non-Linearity	V_A = 2.7 V to 5.5 V		T_A = 25°C	−0.15		+0.25	LSB
		V_A = 2.7 V to 5.5 V		T_MIN ≤ T_A ≤ T_MAX	−0.7		+1	LSB
		V_A = 4.5 V to 5.5 V ⁽⁸⁾		T_A = 25°C			±0.11	LSB
		V_A = 4.5 V to 5.5 V ⁽⁸⁾		T_MIN ≤ T_A ≤ T_MAX			±0.5	LSB
ZE	Zero Code Error	I_OUT = 0		T_A = 25°C			+4	mV
ZE	Zero Code Error	I_OUT = 0		T_MIN ≤ T_A ≤ T_MAX			+15	mV
FSE	Full-Scale Error	I_OUT = 0		T_A = 25°C			−0.06	%FSR
FSE	Full-Scale Error	I_OUT = 0		T_MIN ≤ T_A ≤ T_MAX			−1	%FSR
GE	Gain Error	All ones Loaded to DAC register		T_A = 25°C		−0.1		%FSR
GE	Gain Error	All ones Loaded to DAC register		T_MIN ≤ T_A ≤ T_MAX		±1		%FSR
ZCED	Zero Code Error Drift					−20		µV/°C
TC GE	Gain Error Tempco	V_A = 3 V				−0.7		ppm/°C
TC GE	Gain Error Tempco	V_A = 5 V				−1		ppm/°C
OUTPUT CHARACTERISTICS
	Output Voltage Range⁽⁸⁾	T_MIN ≤ T_A ≤ T_MAX			0		V_A	V
ZCO	Zero Code Output	V_A = 3 V, I_OUT = 10 µA					1.8	mV
		V_A = 3 V, I_OUT = 100 µA					5	mV
		V_A = 5 V, I_OUT = 10 µA					3.7	mV
		V_A = 5 V, I_OUT = 100 µA					5.4	mV
FSO	Full Scale Output	V_A = 3 V, I_OUT = 10 µA					2.997	V
		V_A = 3 V, I_OUT = 100 µA					2.99	V
		V_A = 5 V, I_OUT = 10 µA					4.995	V
		V_A = 5 V, I_OUT = 100 µA					4.992	V
	Maximum Load Capacitance	R_L = ∞					1500	pF
	Maximum Load Capacitance	R_L = 2 kΩ					1500	pF
	DC Output Impedance						1.3	Ohm
I_OS	Output Short Circuit Current	V_A = 5 V, V_OUT = 0 V, Input code = FFFh					−63	mA
		V_A = 3 V, V_OUT = 0 V, Input code = FFFh					−50	mA
		V_A = 5 V, V_OUT = 5 V, Input code = 000h					74	mA
		V_A = 3 V, V_OUT = 3 V, Input code = 000h					53	mA
LOGIC INPUT
I_IN	Input Current ⁽⁸⁾	T_MIN ≤ T_A ≤ T_MAX					±1	µA
V_IL	Input Low Voltage ⁽⁸⁾	V_A = 5 V T_MIN ≤ T_A ≤ T_MAX					0.8	V
V_IL	Input Low Voltage ⁽⁸⁾	V_A = 3 V T_MIN ≤ T_A ≤ T_MAX					0.5	V
V_IH	Input High Voltage ⁽⁸⁾	V_A = 5 V T_MIN ≤ T_A ≤ T_MAX			2.4			V
V_IH	Input High Voltage ⁽⁸⁾	V_A = 3 V T_MIN ≤ T_A ≤ T_MAX			2.1			V
C_IN	Input Capacitance ⁽⁸⁾	T_MIN ≤ T_A ≤ T_MAX					3	pF
POWER REQUIREMENTS
I_A	Supply Current (output unloaded)	Normal Mode f_SCLK = 30 MHz	V_A = 5.5 V	T_A = 25°C			260	µA
			V_A = 5.5 V	T_MIN ≤ T_A ≤ T_MAX			312	µA
			V_A = 3.6 V	T_A = 25°C			177	µA
			V_A = 3.6 V	T_MIN ≤ T_A ≤ T_MAX			217	µA
		Normal Mode f_SCLK = 20 MHz	V_A = 5.5 V	T_A = 25°C			224	µA
			V_A = 5.5 V	T_MIN ≤ T_A ≤ T_MAX			279	µA
			V_A = 3.6 V	T_A = 25°C			158	µA
			V_A = 3.6 V	T_MIN ≤ T_A ≤ T_MAX			197	µA
		Normal Mode f_SCLK = 0	V_A = 5.5 V				153	µA
		Normal Mode f_SCLK = 0	V_A = 3.6 V				118	µA
		All PD Modes, f_SCLK = 30 MHz	V_A = 5 V				84	µA
		All PD Modes, f_SCLK = 30 MHz	V_A = 3 V				42	µA
		All PD Modes, f_SCLK = 20 MHz	V_A = 5 V				56	µA
		All PD Modes, f_SCLK = 20 MHz	V_A = 3 V				28	µA
		All PD Modes, f_SCLK = 0 ⁽⁸⁾	V_A = 5.5 V	T_A = 25°C			0.07	µA
			V_A = 5.5 V	T_MIN ≤ T_A ≤ T_MAX			1	µA
			V_A = 3.6 V	T_A = 25°C			0.04	µA
			V_A = 3.6 V	T_MIN ≤ T_A ≤ T_MAX			1	µA
P_C	Power Consumption (output unloaded)	Normal Mode f_SCLK = 30 MHz	V_A = 5.5 V	T_A = 25°C			1.43	mW
			V_A = 5.5 V	T_MIN ≤ T_A ≤ T_MAX			1.72	mW
			V_A = 3.6 V	T_A = 25°C			0.64	mW
			V_A = 3.6 V	T_MIN ≤ T_A ≤ T_MAX			0.78	mW
		Normal Mode f_SCLK = 20 MHz	V_A = 5.5 V	T_A = 25°C			1.23	mW
			V_A = 5.5 V	T_MIN ≤ T_A ≤ T_MAX			1.53	mW
			V_A = 3.6 V	T_A = 25°C			0.57	mW
			V_A = 3.6 V	T_MIN ≤ T_A ≤ T_MAX			0.71	mW
		Normal Mode f_SCLK = 0	V_A = 5.5 V				0.84	µW
		Normal Mode f_SCLK = 0	V_A = 3.6 V				0.42	µW
		All PD Modes, f_SCLK = 30 MHz	V_A = 5 V				0.42	µW
		All PD Modes, f_SCLK = 30 MHz	V_A = 3 V				0.13	µW
		All PD Modes, f_SCLK = 20 MHz	V_A = 5 V				0.28	µW
		All PD Modes, f_SCLK = 20 MHz	V_A = 3 V				0.08	µW
		All PD Modes, f_SCLK = 0 ⁽⁸⁾	V_A = 5.5 V	T_A = 25°C			0.39	µW
			V_A = 5.5 V	T_MIN ≤ T_A ≤ T_MAX			5.5	µW
			V_A = 3.6 V	T_A = 25°C			0.14	µW
			V_A = 3.6 V	T_MIN ≤ T_A ≤ T_MAX			3.6	µW
I_OUT / I_A	Power Efficiency	I_LOAD = 2 mA	V_A = 5 V			91%
I_OUT / I_A	Power Efficiency	I_LOAD = 2 mA	V_A = 3 V			94%

7.6 AC and Timing Characteristics

PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	UNIT
f_SCLK	SCLK Frequency	T_MIN ≤ T_A ≤ T_MAX					30	MHz
t_s	Output Voltage Settling Time ⁽⁸⁾	400h to C00h code change, R_L = 2 kΩ	C_L ≤ 200 pF	T_A = 25°C			8	µs
			C_L ≤ 200 pF	T_MIN ≤ T_A ≤ T_MAX			10	µs
			C_L = 500 pF			12		µs
		00Fh to FF0h code change, R_L = 2 kΩ	C_L ≤ 200 pF			8		µs
		00Fh to FF0h code change, R_L = 2 kΩ	C_L = 500 pF			12		µs
SR	Output Slew Rate					1		V/µs
	Glitch Impulse	Code change from 800h to 7FFh				12		nV-s
	Digital Feedthrough					0.5		nV-s
t_WU	Wake-Up Time	V_A = 5 V				6		µs
t_WU	Wake-Up Time	V_A = 3 V				39		µs
1/f_SCLK	SCLK Cycle Time	T_MIN ≤ T_A ≤ T_MAX			33			ns
t_H	SCLK High time	T_A = 25°C			5			ns
t_H	SCLK High time	T_MIN ≤ T_A ≤ T_MAX			13			ns
t_L	SCLK Low Time	T_A = 25°C			5			ns
t_L	SCLK Low Time	T_MIN ≤ T_A ≤ T_MAX			13			ns
t_SUCL	Set-up Time SYNC to SCLK Rising Edge	T_A = 25°C			−15			ns
t_SUCL	Set-up Time SYNC to SCLK Rising Edge	T_MIN ≤ T_A ≤ T_MAX			0			ns
t_SUD	Data Set-up Time	T_A = 25°C			2.5			ns
t_SUD	Data Set-up Time	T_MIN ≤ T_A ≤ T_MAX			5			ns
t_DHD	Data Hold Time	T_A = 25°C			2.5			ns
t_DHD	Data Hold Time	T_MIN ≤ T_A ≤ T_MAX			4.5			ns
t_CS	SCLK fall to rise of SYNC	V_A = 5 V		T_A = 25°C	0			ns
		V_A = 5 V		T_MIN ≤ T_A ≤ T_MAX	3			ns
		V_A = 3 V		T_A = 25°C	–2			ns
		V_A = 3 V		T_MIN ≤ T_A ≤ T_MAX	1			ns
t_SYNC	SYNC High Time	2.7 ≤ V_A ≤ 3.6		T_A = 25°C	9			ns
		2.7 ≤ V_A ≤ 3.6		T_MIN ≤ T_A ≤ T_MAX	20			ns
		3.6 ≤ V_A ≤ 5.5		T_A = 25°C	5			ns
		3.6 ≤ V_A ≤ 5.5		T_MIN ≤ T_A ≤ T_MAX	10			ns

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified

(3) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than V_A), the current at that pin must be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

(4) The absolute maximum junction temperature (T_JMAX) for this device is 150°C. The maximum allowable power dissipation is dictated by T_JMAX, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula P_DMAX = (T_JMAX − T_A) / θ_JA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions must always be avoided.

(5) See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices.

(6) The analog inputs are protected as shown below. Input voltage magnitudes up to V_A + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above V_A or below GND by more than 100 mV. For example, if V_A is 2.7V_DC, ensure that −100mV ≤ input voltages ≤2.8V_DC to ensure accurate conversions.
DAC121S101 DAC121S101-Q1 20114904.gif

(7) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).

(8) This parameter is specified by design and/or characterization and is not tested in production.