ZHCSEN8A
NOVEMBER 2014 – January 2016
DS90UH940-Q1
PRODUCTION DATA.
1
特性
2
应用
3
说明
4
应用 图
5
修订历史记录
6
Pin Configurations and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings—JEDEC
7.3
ESD Ratings—IEC and ISO
7.4
Recommended Operating Conditions
7.5
Thermal Information
7.6
DC Electrical Characteristics
7.7
AC Electrical Characteristics
7.8
Timing Requirements for the Serial Control Bus
7.9
Switching Characteristics
7.10
Timing Diagrams and Test Circuits
7.11
Power Sequence
7.12
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
High Speed Forward Channel Data Transfer
8.3.2
Low Speed Back Channel Data Transfer
8.3.3
FPD-Link III Port Register Access
8.3.4
Clock and Output Status
8.3.5
LVCMOS VDDIO Option
8.3.6
Power Down (PDB)
8.3.7
Interrupt Pin — Functional Description and Usage (INTB_IN)
8.3.8
General-purpose I/O
8.3.8.1
GPIO[3:0] and D_GPIO[3:0] Configuration
8.3.8.2
Back Channel Configuration
8.3.8.3
GPIO_REG[8:5] Configuration
8.3.9
SPI Communication
8.3.9.1
SPI Mode Configuration
8.3.9.2
Forward Channel SPI Operation
8.3.9.3
Reverse Channel SPI Operation
8.3.10
Backward Compatibility
8.3.11
Input Equalization
8.3.12
I2S Audio Interface
8.3.12.1
I2S Transport Modes
8.3.12.2
I2S Jitter Cleaning
8.3.12.3
MCLK
8.3.13
HDCP
8.3.13.1
HDCP I2S Audio Encryption
8.3.14
Built-In Self Test (BIST)
8.3.14.1
BIST Configuration And Status
8.3.14.1.1
Sample BIST Sequence
8.3.14.2
Forward Channel and Back Channel Error Checking
8.3.15
Internal Pattern Generation
8.4
Device Functional Modes
8.4.1
Configuration Select
8.4.1.1
1-lane FPD-Link III Input, 4 MIPI lanes Output
8.4.1.2
1-lane FPD-Link III Input, 2 MIPI lanes Output
8.4.1.3
2-lane FPD-Link III Input, 4 MIPI lanes Output
8.4.1.4
2-lane FPD-Link III Input, 2 MIPI lanes Output
8.4.1.5
1- or 2-lane FPD-Link III Input, 2 or 4 MIPI lanes Output in Replicate
8.4.2
MODE_SEL[1:0]
8.4.3
CSI-2 Interface
8.4.4
Input Display Timing
8.4.5
MIPI CSI-2 Output Data Formats
8.4.6
Non-Continuous / Continuous Clock
8.4.7
Ultra Low Power State (ULPS)
8.4.8
CSI-2 Data Identifier
8.5
Programming
8.5.1
Serial Control Bus
8.5.2
Multi-Master Arbitration Support
8.5.3
I2C Restrictions on Multi-Master Operation
8.5.4
Multi-Master Access to Device Registers for Newer FPD-Link III Devices
8.5.5
Multi-Master Access to Device Registers for Older FPD-Link III Devices
8.5.6
Restrictions on Control Channel Direction for Multi-Master Operation
8.6
Register Maps
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
PCB Layout and Power System Considerations
9.2.2.2
CML Interconnect Guidelines
9.2.3
Application Performance Plots
10
Power Supply Recommendations
10.1
Power Up Requirements and PDB Pin
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
器件和文档支持
12.1
文档支持
12.1.1
相关文档
12.2
社区资源
12.3
商标
12.4
静电放电警告
12.5
Glossary
13
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
NKD|64
MPQS032B
散热焊盘机械数据 (封装 | 引脚)
NKD|64
QFND765
订购信息
zhcsen8a_oa
zhcsen8a_pm
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