SN74LVC1G32 Single 2-Input Positive-OR Gate
- SCES219V April 1999 – August 2015 SN74LVC1G32
  
  PRODUCTION DATA.

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DATA SHEET

SN74LVC1G32 Single 2-Input Positive-OR Gate

1 Features

Available in the Ultra-Small 0.64 mm²
Package (DPW) with 0.5-mm Pitch
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5-V
Supports Down Translation to V_CC
Max t_pd of 3.6 ns at 3.3-V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3-V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

2 Applications

AV Receiver
Blu-ray Player and Home Theater
Digital Picture Frame (DPF)
Embedded PC
IP Phone: Wireless
High-Speed Data Acquisition and Generation
Motor Control: High-Voltage
Optical Networking: Video Over Fiber and EPON
Personal Navigation Device (GPS)
Portable Media Player
Private Branch Exchange (PBX)
Server PSU
SSD: Internal and External
TV: LCD/Digital and High-Definition (HDTV)
Telecom Shelter: Power Distribution Unit (PDU), Power Monitoring Unit (PMU), Wireless Battery Monitoring, Remote Electrical Tilt Unit (RET), Remote Radio Unit (RRU), Tower Mounted Amplifier (TMA)
Video Conferencing: IP-Based HD
Vector Signal Analyzer and Generator
WiMAX and Wireless Infrastructure Equipment
Wireless Headset, Keyboard, Mouse, and Repeater

3 Description

This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G32 device performs the Boolean function SN74LVC1G32 ineq_ces219.gif in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad V_CC operating range.

The SN74LVC1G32 device is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 × 0.8 mm.

Device Information⁽¹⁾

DEVICE NAME	PACKAGE (PINS)	BODY SIZE
SN74LVC1G32DBV	SOT-23 (5)	2.90 mm × 2.80 mm
SN74LVC1G32DCK	SC70 (5)	2.00mm × 2.10 mm
SN74LVC1G32DRY	SON (6)	1.45 mm × 1.00 mm
SN74LVC1G32DSF	SON (6)	1.00 mm × 1.00 mm
SN74LVC1G32DPW	X2SON (4)	0.80 mm × 0.80 mm
SN74LVC1G32DRL	SOT (5)	1.60 mm × 1.60 mm
SN74LVC1G32YZP	DSBGA (5)	1.38 mm × 0.88 mm

For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from U Revision (April 2014) to V Revision

Added T_J junction temp spec to Abs Max RatingsGo

Changes from T Revision (March 2014) to U Revision

Updated Features, Description, and Device Information table.Go
Added Pin Functions table. Go
Added Thermal Information table. Go
Added Detailed Description section. Go
Added Application and Implementation section. Go
Added Layout section. Go

Changes from S Revision (July 2013) to T Revision

Updated Features.Go
Added Applications.Go
Added Device Information table.Go
Added DPW Package. Go
Moved T_stg to Handling Ratings table.Go

Changes from R Revision (June 2013) to S Revision

Added parameter values for –40 to 125°C temperature ratings.Go

Changes from Q Revision (November 2012) to R Revision

Deleted Ordering Information table.Go

5 Pin Configuration and Functions

Pin Functions

PIN				DESCRIPTION
NAME	DBV, DCK, DRL, YZP	DRY, DSF	DPW	DESCRIPTION
A	1	1	2	Input
B	2	2	1	Input
GND	3	3	3	Ground
Y	4	4	4	Output
VCC	5	6	5	Power pin
NC	–	5	–	Not connected

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage range		–0.5	6.5	V
V_I	Input voltage range⁽²⁾		–0.5	6.5	V
V_O	Voltage range applied to any output in the high-impedance or power-off state⁽²⁾		–0.5	6.5	V
V_O	Voltage range applied to any output in the high or low state⁽²⁾⁽³⁾		–0.5	V_CC + 0.5	V
I_IK	Input clamp current	V_I < 0		–50	mA
I_OK	Output clamp current	V_O < 0		–50	mA
I_O	Continuous output current			±50	mA
	Continuous current through V_CC or GND			±100	mA
T_J	Junction temperature		–65	150	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The value of V_CC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

PARAMETER		DEFINITION	VAUE		UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000		V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage	Operating	1.65	5.5	V
V_CC	Supply voltage	Data retention only	1.5		V
V_IH	High-level input voltage	V_CC = 1.65 V to 1.95 V	0.65 × V_CC		V
		V_CC = 2.3 V to 2.7 V	1.7
		V_CC = 3 V to 3.6 V	2
		V_CC = 4.5 V to 5.5 V	0.7 × V_CC
V_IL	Low-level input voltage	V_CC = 1.65 V to 1.95 V		0.35 × V_CC	V
		V_CC = 2.3 V to 2.7 V		0.7
		V_CC = 3 V to 3.6 V		0.8
		V_CC = 4.5 V to 5.5 V		0.3 × V_CC
V_I	Input voltage		0	5.5	V
V_O	Output voltage		0	V_CC	V
I_OH	High-level output current	V_CC = 1.65 V		–4	mA
		V_CC = 2.3 V		–8
		V_CC = 3 V		–16
		V_CC = 3 V		–24
		V_CC = 4.5 V		–32
I_OL	Low-level output current	V_CC = 1.65 V		4	mA
		V_CC = 2.3 V		8
		V_CC = 3 V		16
		V_CC = 3 V		24
		V_CC = 4.5 V		32
Δt/Δv	Input transition rise or fall rate	V_CC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V		20	ns/V
		V_CC = 3.3 V ± 0.3 V		10
		V_CC = 5 V ± 0.5 V		5
T_A	Operating free-air temperature	DSBGA package	–40	85	°C
T_A	Operating free-air temperature	All other packages	-40	125	°C

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN74LVC1G32						UNIT
		DBV	DCK	DRL	DRY	YZP	DPW
		5 PINS	5 PINS	5 PINS	6 PINS	5 PINS	4 PINS
R_θJA	Junction-to-ambient thermal resistance	229	278	243	439	130	340	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	164	93	78	277	54	215
R_θJB	Junction-to-board thermal resistance	62	65	78	271	51	294
ψ_JT	Junction-to-top characterization parameter	44	2	10	84	1	41
ψ_JB	Junction-to-board characterization parameter	62	64	77	271	50	294
R_θJCbot	Junction-to-case (bottom) thermal resistance	–	–	–	–	–	250

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		V_CC	–40°C to 85°C			–40°C to 125°C RECOMMENDED			UNIT
PARAMETER		TEST CONDITIONS		V_CC	MIN	TYP⁽¹⁾	MAX	MIN	TYP	MAX	UNIT
V_OH		I_OH = –100 µA		1.65 V to 5.5 V	V_CC – 0.1			V_CC – 0.1			V
		I_OH = –4 mA		1.65 V	1.2			1.2
		I_OH = –8 mA		2.3 V	1.9			1.9
		I_OH = –16 mA		3 V	2.4			2.4
		I_OH = –24 mA		3 V	2.3			2.3
		I_OH = –32 mA		4.5 V	3.8			3.8
V_OL		I_OL = 100 µA		1.65 V to 5.5 V			0.1			0.1	V
		I_OL = 4 mA		1.65 V			0.45			0.45
		I_OL = 8 mA		2.3 V			0.3			0.4
		I_OL = 16 mA		3 V			0.4			0.5
		I_OL = 24 mA		3 V			0.55			0.65
		I_OL = 32 mA		4.5 V			0.55			0.65
I_I	A or B inputs	V_I = 5.5 V or GND		0 to 5.5 V			±5			±5	µA
I_off		V_I or V_O = 5.5 V		0			±10			±25	µA
I_CC		V_I = 5.5 V or GND,	I_O = 0	1.65 V to 5.5 V			10			10	µA
ΔI_CC		One input at V_CC – 0.6 V, Other inputs at V_C_C or GND		3 V to 5.5 V			500			500	µA
C_i		V_I = V_CC or GND		3.3 V		4			4		pF

(1) All typical values are at V_CC = 3.3 V, T_A = 25°C.

6.6 Switching Characteristics, C_L = 15 pF

over recommended operating free-air temperature range, C_L = 15 pF (unless otherwise noted) (see Figure 3)

PARAMETER	FROM (INPUT)	TO (OUTPUT)	–40°C to 85°C								UNIT
			V_CC = 1.8 V ± 0.15 V		V_CC = 2.5 V ± 0.2 V		V_CC = 3.3 V ± 0.3 V		V_CC = 5 V ± 0.5 V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
t_pd	A or B	Y	1.9	7.2	0.8	4.4	0.9	3.6	0.8	3.4	ns

6.7 Switching Characteristics, 1.8 V and 2.5V

over recommended operating free-air temperature range, C_L = 30 pF or 50 pF (unless otherwise noted)⁽¹⁾ (see Figure 4)

PARAMETER	FROM (INPUT)	TO (OUTPUT)	–40°C to 85°C		–40°C to 125°C RECOMMENDED		–40°C to 85°C		–40°C to 125°C RECOMMENDED		UNIT
			V_CC = 1.8 V ± 0.15 V		V_CC = 1.8 V ± 0.15 V		V_CC = 2.5 V ± 0.2 V		V_CC = 2.5 V ± 0.2 V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
t_pd	A or B	Y	2.8	8	2.8	9	1.2	5.5	1.2	6	ns

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

6.8 Switching Characteristics, 3.3 V and 5 V

over recommended operating free-air temperature range, C_L = 30 pF or 50 pF (unless otherwise noted)⁽¹⁾ (see Figure 4)

PARAMETER	FROM (INPUT)	TO (OUTPUT)	–40°C to 85°C		–40°C to 125°C RECOMMENDED		–40°C to 85°C		–40°C to 125°C RECOMMENDED		UNIT
			V_CC = 3.3 V ± 0.3 V		V_CC = 3.3 V ± 0.3 V		V_CC = 5 V ± 0.5 V		V_CC = 5 V ± 0.5 V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
t_pd	A or B	Y	1.1	4.5	1	4	1	4	1	4.5	ns

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested

6.9 Operating Characteristics

T_A = 25°C

PARAMETER			TEST CONDITIONS	V_CC = 1.8 V	V_CC = 2.5 V	V_CC = 3.3 V	V_CC = 5 V	UNIT
PARAMETER			TEST CONDITIONS	TYP	TYP	TYP	TYP	UNIT
C_pd	Power dissipation capacitance		f = 10 MHz	20	20	21	22	pF

6.10 Typical Characteristics

Figure 1. TPD Across Temperature
at 3.3 V V_CC

Figure 2. TPD Across V_CC at 25°C

7 Parameter Measurement Information

Figure 3. Load Circuit and Voltage Waveforms

Figure 4. Load Circuit and Voltage Waveforms

8 Detailed Description

8.1 Overview

The SN74LVC1G32 device contains one 2-input positive OR gate device and performs the Boolean function SN74LVC1G32 ineq_ces219.gif . This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.

8.2 Functional Block Diagram

8.3 Feature Description

Wide operating voltage range.
- Operates from 1.65 V to 5.5 V.
Allows down voltage translation.
Inputs accept voltages to 5.5 V.
I_off feature allows voltages on the inputs and outputs, when V_CC is 0 V.

8.4 Device Functional Modes

Function Table

INPUTS		OUTPUT Y
A	B	OUTPUT Y
H	X	H
X	H	H
L	L	L